Multicycle Paths | STA | Back To Basics

Multicycle Paths | STA | Back To Basics
Hello Everyone,
This video contains information about multicycle paths and how does the timing analysis tool interpret the multicycle constraints.
Some of my other videos are given below:
Can Set Up and Hold Time be negative?
• Can Set Up and Hold Ti...
Set Up Time
• Set Up Time | STA | B...
Hold Time
• Hold Time | STA | Back...
D-Latch & D-Flip Flop
• D-Latch & D-Flip flop.
Find all my videos on Physical Only Cells in the following playlist.
/ @backtobasics5602
Temperature Inversion
• Temperature Inversion ...
Working of MOSFET
• Working of a MOSFET
Antenna Effects
• Antenna Effects | Phys...
Outro Template : zipansion.com/1...
#Multicycle#STA#BackToBasics

[@Mark4Jesus]

To summarize: Multi-cycle path resolution is using timing constraints file to tell the timing analysis tool it is alright to allow an extra cycle. Tell it to calculate the setup based on 2 cycles. Tell it to make sure the min hold time is 1 cycle so it doesn’t get captured too early (i.e. ”n-1”, or 2-1 = 1 cycle in this example). (If I got that wrong please correct me). Thanks for the video!

[@romulox4318]

You are doing a great job on these videos. Thank you for your time and effort. A good topic would be STA with divided clocks and the setup and hold implications. Others could be gated clock checks, and setting insertion delay through elements like a DLL that has a closed loop system to guarantee the delay across corners. Keep up the awesome work.

[@lokeshamara2788]

Very nice explanation buddy. Since hold doesn't depend on the time period of the clock, it should be performed at the same edge. What u told is correct.

[@anmr9480]

Nicely explained. Brief topic and briefly explained. Keep going

[@prasannakulkarni8187]

Very short and crisp.. Too good

[@ashwathk3449]

simple and to the point , thanks for the lesson

[@krishnachaitanya2737]

thnaq for u easy way of explanation

[@srilakshmipeteti8087]

Thank you, Thank you soo much!!

[@ravikumarmalamanti3871]

Appreciating Your moto which is amazing and topics are very useful to revise PD basics... Please do one video on mutually exclusive clocks.

[@priyankaa6749]

Mam, Very nice explanation. Thank you for your value input

[@bathulanarendra8988]

Please tell by taking with low frequency and high frequency clocks at launch and capture flops and viceverssa

[@akashlakhera3727]

nice explaination , also please make video on time borrowing of latch

[@saiprasathg7591]

Hi , all your videos are really helpful to learn VLSI in simple and easy to understand , post some STA concepts like Input /output delay with calculation

[@backtobasics5602]

Thanks. Sure, will try to post more STA videos.

[@venugopalreddygogireddy716]

madam ,thank you very much

[@avinashvinith84]

Good explanation as always.

[@ashwinis2838]

Please make video on all the timing exceptions

[@satyakittu200]

Can you pls explain setup and hold checks for half cycle path

[@TarunKumar-px1yb]

Hello Ma'am, The topic is explained in a very simple and nice way. My question is do we need to do any changes in the hardware part also (RTL Design using VHDL) to apply these constraints properly like clock gating or data path gating ?

[@vishaltakle5465]

Can it be advantage of given multicycle path in my design ?

[@anime_sensei_squad]

Thank you Ma'am :)

[@RelentlessLad]

Please do on OCV, PVT, exception. Wish you were my BTech tutor

[@sanjusingertelugu9862]

nice mam explains about the multi clock cycle?

[@kunliu5004]

Madam, thank for tutoring. I am still confusing about the hold time check. Why do we check hold time at 10ns instead of 30ns? The capture flip-flops received the data at 30ns. Therefore the hold time should be check at 30ns. Why the setup time and hold time didn't check the same clock edge?

[@bertonglagalag706]

thank you maan. .im new freind

[@nephewniece3312]

Wt is the diff between multi cycle path and set_maxdelay

[@rupeshshelke2181]

ma'am, can you please make a video on the example of STA

[@rjeyapaul]

Good explanations and presentation. Suggestion : please add content which is critical to ensure that multicycle paths as a constraint on a design is correct and not wrong otherwise issues will be found only in Gate level Sims. E.g. it is important for the design to break the clock path as a two cycle path instead of the current one cycle path. The capture combo needs to be anded with a pulse generated at divby2 clock frequency. If not done, there is a chance of seeing a delay at 10ns on a particular Pvt scenario(not a slow case) and causing a metastability violation at capture flop

[@AravindKumar-s9e]

Very nice

[@prakashsamraj2653]

Hai mam please explain phase shift and cycle adjustment with respect to lead to lead & & trailing to trailing & & lead to trail and trail to lead paths

[@akshayrastogi4841]

Why do we check hold on same edge ?

[@backtobasics5602]

It is explained in the hold time video