How can the setup and hold time be negative ??

[@kamleshraiter658]

This is probably a misconception. Hold and setup time are property of flip-flop and they remain fixed and can't be changed. The only thing that is changing is the timing equations values due delays, clock to Q and clock skew

[@TheGreatShawnY]

Thanks for your effort of explaining! Merry Christmas and Happy New Year!

[@muggullasairam8442]

Before watching this video i suggest go through internal circuit for a flop.

[@TechnicalBytes]

Thanks for sharing your views!

[@mukulsharma8616]

Will you please make a video on concept of pipeline in RTL Design, thanks and keep up the good work 👍

[@TechnicalBytes]

Will try

[@rockingstone7700]

Sir when delay is being provided to clock then why it is shifted left in timing diagram.... It should be shifted towards right.... Plz clarify this

[@messiweltmeista]

I was thinking exact the same thing. When the clock input is delayed, it should come later, not earlier

[@GregoriousApartment]

see notations carefully

[@rockingstone7700]

@@GregoriousApartment I have watched thoroughly if u have understood then atleast tell the crux behind it ....hope u under my question what I have asked

[@alvinaug3844]

Yes, same I also think

[@meenugarg1102]

Nice explanation

[@TechnicalBytes]

Thank you

[@faneeshbansal]

Sir hold time can be negative but setup time will always be positive