Comparative Deep-Dive: Zen vs. Bulldozer Architectures

[@LTXwooshie]

Real science discussion. I like these videos.

[@xavierrodriguez7657]

While these technical videos may not be the most exciting for everyone they are super interesting to me. Even more so than the generic gpu review or build log

[@tohothewriter8002]

I second that!

[@Xaltar_]

Great video and thanks for delving deeper into the history of Integer and FPU units. It's always nice to see a content creator pay attention to their comments and learn from them where applicable.

[@thegreatmilkguitar]

I’ve actually wanted to know this for a while, thanks. Could you maybe do a video explaining what cpu cache sizes are/what the cache does? Honestly i’d love a “what makes a cpu fast” vid from you if ever possible. Thanks again for the great content and hard work 👍🏾

[@GregSalazar]

Thanks for watching!

[@aluminumman897]

That's a great video idea, I'd like to see it too.

[@mduckernz]

AdoredTV has a recent video on cache which I can recommend

[@mduckernz]

@@Tegridy-TOG Yup this is a good summary for the basics. There is also cache coherency policy and eviction policy (e.g. "victim", "inclusive" etc) and associativity (e.g. "8-way") and a lot more. But you covered the most important ones, or at least, the ones consumers will tend to see advertised.

[@bobhumplick4213]

fun fact: those drop in fpus werent fpus at all. they were complete cpus that turned off the cpu in the system and took its place. thats why you could put cpus in the fpu slot(x87) of systems like 486's and upgrade them to 586's or pentiums or whatever. so they just turned off the cpu you had and replaced it with a new one. this gave a lot of other cpu makers a foothold to start selling cpu's like cyrix and evergreen etc. amd did some of this but they really got their start with x86 when ibm forced intel to find a second source supplier (in case they couldnt meet demand etc). they went with amd and essentially handed over amd the plans for their chip. or at least the masks

[@tohothewriter8002]

According to the techquickie video on "the history of AMD", intel asked them to basically help with chip production(back when AMD owned fabs) and eventually reverse engineered the manufacturing process and start making their own product. Go watch the video, it's really interesting and does a pretty good job of explaining how far back the two companies have been at odds with eachother, in a friendly competitive way of course.

[@AshenTechDotCom]

not always true, in the 386 days for example, if you added a cyrex x87 chip, it was NOT a full cpu, and could NOT function without a 386 or 486 processor along side... for 486 gen stuff, thats 100% true, in most cases, its just a full cpu upgrade, even if the board has 2 sockets/socketed chips, though, there are a few cases where companies used 486sx cores paired with a socket for a 387 chip, that was NOT a full cpu, in the case of some HP "workstation" systems they used full 486DX chips, and had a socketed FPU as well, a retired HP engineer explained that, the cyrex x87 chips, actually had better FPU perf for many apps vs the intel onboard FPU, and some software could actually use both at once, he didnt go beyond to explain what software but, he also explained a system i had come into ownership of.. an old HP server, it had a chip i had never seen before, a 80385 cpu, as well as a 386dx40, and 2 FPU units, as well as a metric fukton of 30pin sim slots(ram), all of it on a card that plugged into the bottom of the system, the "motherboard" was really just a back plane for that card.... it had 2 HUGE MFM hdd's and one HUGE SCSI drive(take up 3x5.25bays each...), it was HUGE... and he got me the disks so we could configure its bios... since it required booting from a disk and running the config software to change bios settings at all...(horrible design...) he ended up buying it off me because...he was one of the guys who designed that monstrosity... Still, never seen a 385.... except in those systems... but also, had a retired intel tech tell me, it was a real, legit thing... he didnt know details but... he remembered it from parts lists that only shipped to OEM's never to retail.

[@kingeling]

Pretty sure it wasn't always the case

[@tohothewriter8002]

This video is great! Answers many of the questions I had for myself about what differenciated the Zen architecture from Bulldozer/Excavator back in late 2017 for a class project I was working on. Amazing and very well detailed explanation of used terminology, major concepts and pretty much everything else in between.

[@AlexSeesing]

Now make more of this much appreciated content. More science. More tech background info. More real SC. Moar!

[@lamchester1]

Awesome to see a video like this. A few comments: 1. Nitpicking on bd fetch/decode - it's two instructions/thread/cycle on average, if two threads are active (fetch/decode serve each thread every other cycle). If only one thread is active, it can get a full four instructions/cycle 2. Memory/lsu explanation was confusing so here's my take on how a load or store is processed: -The instruction gets an entry in reorder buffer and an entry in the LSU's load or store buffer, depending on whether it's a load or store -The AGU calculates the physical address -For loads, if the address matches that of a previous store in the store buffer, that store's value is forwarded to the load instruction's result. - L1D cache tags are checked to see if the address is cached. If so, for loads the value comes from L1D (4 cycles). For stores, the value is written both to L1D and L2, because Bulldozer's L1D is write- through. Since L2 write bandwidth and latency is quite poor on Bulldozer, there's a 4K write-coalescing cache before the L2 that attempts to batch writes. -If L1D miss, L2 is checked. L2 cache latency is about 20 cycles on Bulldozer -If L2 miss, a request is sent to the integrated northbridge, which has the L3 cache (87 cycle latency) and memory controllers. If L3 miss, you get main memory access 3. Caches can contain data you haven't accessed before, because of prefetching. Prefetchers try to get the right data into cache before you see the load instruction (works well if your memory access is predictable) 4. What rename/allocate actually does is to map the smaller set of amd64 registers to the CPU's register file, eliminating false dependencies along the way. i.e.: instructions: a = b + c store a to address d a = b * 2 store a to address d renamer sends this to the rob (overly simplified, b and c would have previously been renamed as well) r1 = b + c store r1 to address d r2 = b * 2 store r2 to address d now the scheduler can dispatch (r1 = b + c) and (r2 = b * 2) in parallel to the two ALUs. stores can then go to the AGUs in parallel, though the LSU can only do one store per cycle in bulldozer 5. Bulldozer's shared FPU isn't that big of a deal. IMO it was the anemic 2 ALUs per core, further cripped by a bad cache hierarchy that made bulldozer bad. Assuming fp instructions are in play, a bulldozer thread can dispatch 2x ALU + 2x AGU + 2x FP add or mul, which is similar to what say intel haswell can do (2x ALU + 2x ALU/ FP add or mul + 2x load AGU + 1x store AGU). If you only consider integer, it's bulldozer's 2x ALU + 2x AGU vs sandy bridge's 3x ALU + 2x AGU. Sandy bridge also has bigger out-of-order queues and a better cache system so bulldozer has to go home crying. So intel (and ryzen) are better because their SMT design means a single thread can get all the resources when there's only one thread active, while bulldozer's separate integer clusters were each weak and thus hurt single thread performance. 6. SMT just means multiple threads running in one core. I'm not sure what you mean by prioritize - with ryzen (and intel) the schedulers can't prioritize one thread over another. AFAIK it's just oldest instructions ready to execute. In that sense the scheduler itself isn't any more efficient. It just hopefully gets more independent instructions and thus more opportunities for parallel dispatch, which allows more efficient use of processor resources when both threads are not bottlenecked on any competitively shared resource. "sends redundancies to the retire queue" - not sure what you mean by that. do you mean move elimination, where the renamer just takes care of a register to register move by messing with its architectural -> physical register mapping, so no 'real' execution resources get used? in all cases instructions will still occupy space on the retire queue until they're retired

[@lamchester1]

I would love to see another video going into even more detail. There's a lot of info on AMD's architectures in their software optimization manuals, at developer.amd.com/resources/developer-guides-manuals/ 15h is the bulldozer family, 17h is ryzen, and 16h is jaguar www.agner.org/optimize/microarchitecture.pdf is also an excellent reference Finally, you can use AMD's codexl (or old codeanalyst on bulldozer) at github.com/GPUOpen-Tools/CodeXL to read CPU performance counters, and see what exactly a specific program or benchmark might be bottlenecking on. For intel CPUs, you can use github.com/opcm/pcm

[@JP_Stone]

Like the technical videos good stuff and very interesting. Not a lot of people in the KZbin tech space dong deep dives into the how and why of computing. Hope to see more in the future. Thanks Greg.

[@CaveyMoth]

"This is going to get technical." [Pastes pictures of DRAM modules on screen for The Verge fans who don't even know how to build a PC]

[@mduckernz]

DRAM slathered with thermal paste ... or liquid metal 😱

[@CaveyMoth]

@@mduckernz Mmmmmmmmmmmmmmmmm.

[@Thewickedjon]

this is the type of video that makes your channel unique. i wish I could do more than like to make you understand this is what people REALLY want to see from you

[@wayne577]

I wish more of the larger tech tubers would get into the dirty technicalities and building blocks of components. As a computer engineering student, videos like this fascinate me while I'm taking classes like microprocessor architectures and operating systems.

[@QuickNETTech]

Glad to see this kind of content make a comeback. More of these please!

[@MatrixJockey]

I've been wondering when you would bring back your technical videos. I dig the knowledge brain rush.

[@John-np2bf]

This has to be the best channels for learning new things whether you're new to PC's or you're a cyber pimp. I've been building and working with them since 486 days and I pick up new things in every video. And Greg doesn't use clickbait titles to draw an audience. Very refreshing. Thanks Greg!

[@KodySalad99]

I've been waiting for this video for so long, I'm glad you were able to make it. Sorry I haven't been around lately, been crazy busy. I'll try to be more active tho! Miss ya Greg!

[@cwbh10]

Good stuff man! As a senior ECE rn, I love hearing the more technical stuff. The builds and benchmarks get old pretty fast imo

[@leexgx]

correct reasons why cinebench is reporting it is 4 core 8 thread is because it's what Windows 8 and higher reports that way for intended reasons (other apps say like cpu-z did not read the os and used its own database witch partly incorrectly shows it as 8 core when it should be 4 modules 8 threads in cpu-z not 8 core, 8 threads) windows 8 and higher had 2 updates, first one was issued to forced it to work as 4 core 8 thread to make sure the task Scheduler treats it like HT/SMT (due to shared nature the cores operated more like ht and programs run upto 10-50% slower if 2 different threads used the same module, this is why this fix was implemented) second update was to make sure it loaded 1 thread per module starting from module 1 then 2-3-4 because bulldozer lacked per module independent power down states it only supported staggered power down and up states so if module 1 2 3 was idle but module 4 was in use it had to fully power up module 1-2-3 to make module 4 goto full power state, this fix made sure work was placed on first modules first so other modules could goto sleep and power down (I forgot if bulldozer had turbo boost but if it did it would also allow it to clock higher on first to modules)

[@Jerig128]

Great return to form! I'm helping a friend learn computers and this is a perfect modern day explanation which pairs perfectly with the old school stuff he's learning about

[@xero110]

Glad to see the info from the comments making it into the videos.

[@davidbreeden81]

I've been a channel subscriber for about 18 months and I love these technical videos. They harken back to the early days of Science Studio. They're what drew me to your channel in the first place and what has kept me here.

[@GregSalazar]

Thanks, Dave!

[@SonGoku-97]

love these kinds of videos, good work man

[@LoL768491]

This is the heart of the channel as you said. No1 makes content like THIS. and you abso-fucking-lutely NAILED it! Gj!

[@imtechfreak1800]

I would eagerly watch this several times to find out any details, thanks MR. Scientist, I am even willing to not to skip the ads for this one so you have more ads time cuz I know this level of details needs too much work and big BAAALLLS at the same time!!

[@GregSalazar]

Thank you! If you catch anything incorrect in this video, let me know!

[@pixel_vengeur391]

Just a small detail I maybe overheard, but an ALU can also perform boolean operations (AND, OR) :)

[@thepointblank213]

Videos like this is actually why I subscribed. Thanks for getting back to your roots.

[@meddlin]

Love it when you go over this type of content! It's a nice "bridge of understanding" between the hardware-heavy GN (which is good!) and the more PC-oriented channels (also good!).

[@rebel1988us]

I love these videos! Thank you, I was literally just arguing with someone the definition of an Intergrated Graphics Processor the other day. You are awesome at explaining this is in a somewhat understandable way.

[@GregSalazar]

Thanks, Trev!

[@simber6934]

Zen almighty grant us clock speed!

[@koopahermit]

@@colin8601 Nvidia doesn't make x86 CPUs.

[@BavarianM]

@@colin8601 You know jack shit

[@badass6300]

@@colin8601 Well considering that Zen is a better architecture than coffeelake, but the process node it was on by Global Foundry(12/14nm) is meant for low power, low transistor count, small die mobile SoCs, clock speeds and voltage scaled poorly with the relatively big die sizes of Zen(Big Compared to ARM SoCs). While on the other hand Intel have confirmed that 1st gen 10nm process node will be slower than 14nm++, and it will take at least 1-2 more generations of 10nm CPUs to get to there, on the other hand TSMC's 7nm will clock better than Global Foundry's(Samsung Licensed) 12/14nm.

[@CaveyMoth]

I really hope that Zen 2 won't feature 1.4 Ghz base clocks.

[@badass6300]

@@CaveyMoth why?

[@sxxxychocolate]

great vid. i love how good your vids look lately-super sharp compared to others. must be the camera you use. keep them coming. Anyway with all the people upgrading, it would be great to hear your views/options on what to do with the old systems/parts left over. i mean hdds. psu, fans, case and possibly graphics cards may be reused in another build. but some people might just build a whole new system. so what can you do with the old one if you decide to keep it together? is it worth it? what other purposes can you use an old system for? backup?

[@WinnieBlue]

Greg just going to say I love your camera setup right now. That shot is as clean as your PC builds.

[@GregSalazar]

I really appreciate that!

[@KooYu]

A 'strictly science' video once in a while is so refreshing. Not that I don't enjoy the rest of the content, mind you. But it'w this channel's 'signature style'.

[@CoalitionGaming]

Knowing this kind of stuff is one of the reasons I love computers, tech, CPUs, hardware, all that.

[@trandel]

I love this type of content, it satisfies the inner geek. Even though we've had die shrinkage I think we're nearing the end of this type of architecture. ISA for X86 will be over taken by RISC ISA's either ARM or RISC-V. X86 is far too inefficient to make to many head room gains moving forward. Although I'm not to sure about the comment about the size of L2 cache slowing down performance, surely this is dependent on the tasks? So I can understand a home PC being limited by multiple varied instructions but not so in a NAS or Print server for instance that still may have lots of instructions but little variation.

[@marcobonera838]

Oh, I see you also watched coreteks :D

[@The_Nihl]

x86 ISA processors desktop are CISC, RISCc operate also within x86 type of instructions, just vastly reduced to most common ones. RISC mean Reduced Instruction Set Computer. CISC means Complex Instruction Set Computer. modern x86 CPUs does CISC to RISC micro operations coversion, break large complex instruction into throughput of RISC type of calculations, therefore are vastly faster in massive and complex workloads than any RISC, small and efficient by its nature, ever could be. RISC and CISC been coexisting from decades, neither one gonna overtake any. What may happen, is that in future we will go into hybrid 3D stacked processing units, incorporating both RISC and CISC type of compute cores.

[@trandel]

@@The_Nihl I think you might like the following article www.eejournal.com/article/risc-v-aims-for-world-domination/ I'm also aware of Intel's Foveros 3D stacked Silicon project. X86 has been modified to improve performance in splitting CISC instructions into RISC and branch predictors (Spector/Meltdown not withstanding). And to some degree 3D stacking may help to keep X86 relevant in the short term. But I still think the biggest issues to overcome is latency, heat and subsequent power draw. I personally think we're far more likely to see ARM and RISC-V SOCs assisted by AI Quantum Cloud computers in the future. We can see Apple Already moving all their products to their ARM based processors in the Next couple of years as an example. Does that mean X86 will die? Not entirely because we still have a lot of legacy systems. But the needs of the average consumer will make their need to access these legacy systems few and fewer over time.

[@ahmetrefikeryilmaz4432]

have been seeing him around, probably watched lotsa videos of him in the years. This video however, is the one that made me subscribe. Please do continue doing these.

[@Silveraga]

Happy to see a new technical video ❤️ well done

[@avglebowski]

Finally I learn something from KZbin, miss these types of videos.

[@dtsdigitalden5023]

A nice return to form. That was a clear, and easy to understand, breakdown of the "core" (hah) differences.

[@jaredchong4070]

Try explaining perceptron branch pridictor from zen architectures. Also , amazing video

[@blazetownsend8785]

The FM2 and FM2+ baords supported the A series processors, which were mostly based off the bulldozer series, but had IGP.

[@hi_tech_reptiles]

More! Give us more! I love this deep dive stuff on hardware. I'd love one between nvidia and AMD GPUs, both as a chip and as full pcb set up etc. Or whatever else!

[@MrJason005]

Maybe you can do a video explaining what instructions/assembly are using an old intel 8088 processor and a breadboard

[@boondoc001]

This is definitely technical. You know I had this very question about the channel name so I'm glad you answered it. I was lost about 2 minutes in lol but I stayed for the whole 12

[@peterjansen4826]

I prefer another perspective for integers vs. floating point. You choose where you want a higher level of accuracy, between two numbers (floating point) or having a much larger reach but being restricted to only whole numbers. The number of bits determines how many values are possible, you sacrifice reach to get more accuracy or you sacrifice accuracy to get more reach and that is required because you only have 2^n values with n = number of bits. Greg, I can tell that you did your research. I studied introductory computer science with a focus on architecture.

[@ashberic]

when can we let go of our pants?

[@pushbaner5219]

please do more like this...loved it!!

[@Scitch87]

Have a headache, am coughing my lungs out and am on meds. Wanted to go to bed then saw your vid. Very good video. Detailed and good explanations with diagrams. Didn't understand a word you said. 12/10 would watch again.

[@GregSalazar]

I appreciate it! And don't worry. Much of this required several days worth of researching. Sometimes, I'd reread a sentence 5 or 6 times before it clicked.

[@Scitch87]

@@GregSalazar that's good to know! I will watch it again later so maybe i'll understand your explanations then. Really appreciate the work you put into this and it's refreshing to actually see someone explain the workings of the CPUs instead of just benchmarking them. :)

[@hjups]

You didn't quite get the block diagram comments about SMT correct - most likely because the blocks were missing in the Bulldozer block diagram. Both Bulldozer and Zen have Rename / Allocator blocks, as well as Retirement Queues / Re-order buffers (aka graduation unit). While those blocks are needed to perform SMT / Hyperthreading, they are needed for a more fundamental scheme in modern computing - out of order execution (OOE). The Rename / Allocator block basically allocates registers addresses for following instructions. It's easier to understand for a RISC architecture like MIPS or PPC, but the concept still applies. Lets say you want to execute the following instructions: (1) R3 = R1 + R2, (2) R4 = R1 * R3, (3) R4 = R2 + $0x200, (4) R5 = Memory[ R4]. There is a dependency there between (1) and (2), and (3) and (4). Also, (2), (3), and (4) all use R4 some as sources and some as results. Without OOE, the processor would have to stall to wait for each instruction to complete. With OOE, the first thing we can do is rename the registers, so (3) and (4) become: (3) R8 = R2 + $0x200, (4) R5 = Memory[ R8], which is what the rename block does. It can also be referred to as an allocator because it is allocating or reserving registers. As a side note, for a MIPS / ARM / PPC architecture with OOE, they have 32 logical registers, but the architecture will usually have 64+ registers, for renaming. So logical R1 can be any of the 64 (the job of the renamer). Now with the registers renamed, we can execute (1) and (3) at the same time, followed by (2) and (4) at at the same time (so twice as fast). But then we get into a problem with logical precision (are the instructions issued in order). Since we want the CPU to execute the instructions in the order it receives them, but also don't want the CPU to be idle waiting on an instruction, as long as we respect data dependencies, we can place the results into a Re-order buffer (ROB), and commit the instructions once the execution order is complete. So in the example above, lets say every instruction takes 1 cycle, except multiply which takes 2, and we have a ROB of size 4. So if (1) and (3) execute together, in the next cycle, the ROB will look like [(1) -- (3) -- ], Then the following cycle when the load completes it will look like [(1) -- (3) (4) ], but none of them have been committed yet (anything that relies on R3 for example will have to wait). Then the next cycle when (2) completes, the ROB looks like [(1) (2) (3) (4)], which is followed by an in-order commit of each instruction (modification of RAM or the internal register file). If you are interested in learning more about how this works, do a search for the IBM PPC Gekko Manual (the CPU that was used in the Nintendo Gamecube). It's an early OOE processor (though it calls itself a super-scalar), which has a lot of detailed descriptions and examples which explain the Renamer and the ROB. It also did not support SMT / Hyperthreading, but did need these components. One final note in regards to units. The ALUs also do integer division and multiplication, though not all ALUs do so. If you look at the block diagrams, you will see they say things like "branch", "IMUL", "IDIV". Those are extra operations besides add / subtract, shifts, and logical ops. So if you wanted to schedule a division, it would have to be on a specific ALU which supports IDIV (integer division). Similarly for computing a branch, it needs to be on a Branch ALU.

[@GregSalazar]

My man! Wanna help me with this next vid? 😉

[@hjups]

​@@GregSalazar Sure, if you need someone to help fact check / clarify something from a computer architecture perspective. I should mention that I am not an expert on AMD / Intel architecture, it's mostly just modern computer architecture schemes / theory (though the theory hasn't changed significantly since the early 2000s).

[@xidentity872]

as someone in parallel programming class, i think this will be helpful for when i want to optimize my assignments with respect to architectural specific implementations

[@karlkingofducks5764]

Give us more of this, great content!

[@jacobstraessle5874]

Reminds me of the classes I had to take whenever a new model of televisions came out. I was an in home TV repair tech before retirement. Technical is fine with me. That is one of the reasons I subscribed to your channel.

[@GregSalazar]

Glad you enjoyed it, Jacob!

[@Chemy.]

You said diving, I almost believed that your hoodie was with the diving flag!

[@paxdriver]

Much appreciate the details, my fav ep yet. Thanks much, keep it up

[@deepakmohapatra7416]

so according to what i learnt from this lesson is my A10-7700K advertised as 4 core Cpu while windows task manager and Cinebench show it as 2 core 4 thread cpu and also playing with core leveling mode in BIOS of A88XM-A Motherboard it has been identified as a 2 core 2 thread Amd A4-7350 something like that and 1 core 1 thread/2 thread Amd K2 processor (As per CPU-Z). but Put it in Automatic mode in Core leveling more and it is 4 core CPU (2 core 4 thread).

[@AshenTechDotCom]

and engineer studied the dozer/driver chips, and found the worst flaw to the perf was how slow the L3, its closer to ram then on die cache in actual perf, the shared resources were less of an issue then other design flaws that could have been addressed with some hand tuning rather then using software to optimize the design automatically... the more you learn about the design and why it had issues the more you just shake your head and ask "why didnt they just hire jim keller....again.....sooner..."

[@earlmcnulty4665]

These kind of videos you put out are my favorite :)

[@LarsBars17]

Great video! Really interesting deep dive.

[@wartrent2]

Thanks Greg! I thought i already knew all you'd say, but it seems I've learned a few new things :D

[@s4ecki]

love these videos ... as you said it's where you started and why I subscribed

[@gloriousptr]

Really explained well, I appreciate your time investment in researching the architecture working and differences

[@theblackmamba190ify]

Love it bro, this is why I subscribed.

[@mrsasshole]

Love these kinds of videos. Great work.

[@GregSalazar]

Thanks for watching!

[@RiccardWoW]

Well done man! I really like this kind of videos

[@mak_ev]

Thanks for the video, that's a great job! Still using FX-8320 as my daily driver and video editing machine and it runs pretty OK!

[@GregSalazar]

Thanks for watching!

[@georgeindestructible]

Is there a way to make the FP Scheduler calculate Integer-type math(use some kind of dedicated rounding decoder?) when it just doesn't do much work in order to assist the Integer Scheduler resulting into more Integer-type calculation throughput or is this a thing already inside like SMT-HT?

[@bullseyestrat]

From personal experience I upgraded from a FX-8350 to a Ryzen 2600. Through benchmarks like CPU Z and Cinebench the Ryzen 2600 is over twice as fast while taking in a max tdp of 65w compared to the 8350's 125w. Kind of crazy what 6 years or so can do with the processors.

[@articletwelve8590]

I love learning about architechture... its like building a lil city, streets, shops, highways... lol :) learned a lot, thanks again! Zen 3 ftw!

[@WGAPGaming]

Bulldozer is Trash Zen is Pushing intel to think

[@WGAPGaming]

@⠀ yes Bulldozer was its own worst enemy

[@wing0zero]

You can also argue Bulldozer and Intel forced AMD to think🤔

[@WGAPGaming]

@@wing0zero very true

[@CaveyMoth]

Ryzen allowed us to...Ryzen...to our potential. I don't think I did that right.

[@WGAPGaming]

Cavey Möth 😂😂

[@andrewlawrence5299]

Rewatching for Zen 3 launch. Very amazing how far AMD has come.

[@danielmdax]

Hey, can you do the same comparing APUs? Raven Ridge (Zen + Vega [GCN 5]) vs Bristol Ridge (Excavator mk2 + GCN 3). I believe Excavator is a 28nm die shrink (from 32nm) and integrates some more advanced features on the CPU (MMX?)

[@jpitt916]

Great detail, love this deep dive!

[@marijnbuitenweg]

Well explained and just as dense as it should be!

[@shadowjulien5]

These may already exist, but have you done a similar deep dive on Intel Architecture? (I'm about to watch the "What the Heck is Hyper Threading video so you can shame me if it's there lol) but if not you should do one of these for Sandy Bridge to Haswell to Skylake!

[@jdmaltezza]

Good job. I love tech spec videos.

[@otisthe1410]

Now your speaking my dialect! I liked hearing all that technical stuff

[@kakarroto007]

Thanks, Greg. That was pretty informative.

[@GregSalazar]

Thanks for watching!

[@Epicmango7]

Learning with Greg. 10 dislikes from people who didn't understand much. I didn't either but I still liked the video.

[@badnewsbruner]

More of these videos!!

[@OlettaLiano]

Good video, thanks. I like learning more about tech things.

[@TopRacer2002]

OK, now can you explain that again but this time really slowly... 😂 😂 😂. Great video Greg.

[@zarf4219]

Can we get a Zen 2 vs Zen comparison video

[@TheVillainOfTheYear]

All of the good tech tuber channels should continue to do builds, reviews, etc., but each should have their own reason for existing. Architecture deep dives is your thing. More please!

[@hi_tech_reptiles]

Is the small cache a factor as why it likes fast RAM....?

[@futurepastnow]

While the AM3+ FX-81xx and FX-83xx Bulldozer/Excavator chips lacked integrated graphics, AMD *did* make APUs using 'Dozer based cores. These used the FM2 and FM2+ sockets and for some reason they just released a new one for AM4 (the A6-9400). I can't imagine why anyone would buy it.

[@Beehj84]

If this is the heart of ScienceStudio then more ScienceStudio please! Great video Greg. Cheers

[@johnlpz2806]

You got videos of IPC improvement of amd zen vs intel 7th,8th OR 9th gen. I guess what will do. Thanks

[@cattycyoutube]

I enjoy these kinds of videos, even if I don't quite get what you're talking about.

[@SpeedWeed97]

i think the best way to understand this video is watching it at 0.75.. so much info in so little time

[@TheBoltcranck]

good ol' type of content!

[@queegfivehundred8197]

My home server has an FX-8320 without a discrete GPU... the graphics in the 760G chipset is too old to support resolutions (for the windows desktop) much above 1080p.

[@iamthenegative1]

wheres that hoodie from?

[@Brian_Buckley]

Love this!!!

[@spacekek8197]

Is there a way to get annumber for the ipc?

[@NizarElZarif]

Space Kek IPC is not constant. It varies by workload. It is the number of instructions retired divided by the clock. The theoretical maximum is 4 for current intel and amd cpu however the upcoming intel icelake will have a mixmum of five. This number comes from how wide is the decoder. So current intel and amd cpu only decode 4 instructions at a clock cycle (per core). but just because you can decode an instruction does not mean you can execute it. To measure an IPC of a program the easiest way is to use linux perf_events tools. A lot of distribution have this tool pre installed. This tool will attach to a process and use internal performance counter to get you the IPC and other metrics (like cache misses and branch misses). Developers users this tool to diagnose performance problems within their codes.

[@mdwahidsadiq2769]

this type of video should be continued.

[@Williammcqueen52]

Please more. GPU Arc next?

[@Baphangelus]

hey can i ask why dont you record in 4k? my tv displays blurry 1080p :s

[@LiLBitsDK]

get a better tv with a good upscaler = solved

[@raiyantajwar1564]

I am a bit early... been a long time since I've been this early honestly... I remember watching your videos in the early days of the channel. Been around for a long time. and then I stopped watching altogether... don't know what happened or how time passed but it's been a year I think... Feels good to be back on 'Salazar Studio' xD

[@GregSalazar]

Thanks for reminding me of our 'Salazar Studio' days 😂

[@marcobonera838]

Very nice and informative video! Also, what the hell is an AGU?? 🙃

[@The_Nihl]

Address Generator Unit. It generate addresses for memory banks to read/write data from it.

[@marcobonera838]

@@The_Nihl thanks

[@Sgtcanadian]

Go deeper. Full workflows in both architectures