DDR4 Part 2

[@tedsdroneworld558]

Thanks, Your DDR4 part1 and part2 has allot of very helpful information. Your micron articles referenced were also very helpful.

[@hudsonv1962]

Great vid, you simplify these sorts of things very well

[@vaualbus]

to bad you di not update more video, they were interesting!

[@Suryaofficial691]

Hi sir , What is rise time and fall time of DDR4. Is the TdiVW is sum of Set up Time and Hold time ? Then the sum rise time and fall time is TdiPW-TdiVW?

[@tfoxwa]

Rise / fall / valid pulse width depends on the exact speed specification of the part you are using. I would refer you to a Micron Data sheet for the part you are going to use. In addition the rise / fall will be dependent upon the load etc. Your only choice is to design very conservatively ( and hope it works) or simulate the circuit with appropriate tools.

[@Suryaofficial691]

@@tfoxwa to set up Eye mask for the simulation needs rise and fall time and set up and hold times for DDR4 at the receiving Mask

[@tfoxwa]

@@Suryaofficial691 The eye mask comes from the receiver specification. The rise and fall time is a result of the drive strength, receiver load, and reflections. That is a result of the interaction between the driver model and the path simulation including the actual input impedance of the receiver...which comes out of the receiver model. The receiver model spec is either from the manufacturers specification data or from the JEDEC specification.

[@Blue.star1]

I dont recommend nor used these high speed design in critical military , aero space , applications , super computers don't use less than 80nm design and noisy ddr 4 running at 2 Ghz

[@Blue.star1]

It's a mess routing now a days

[@tfoxwa]

Better DDR4 than DDR2