Designing a Simple Voting Machine using FPGAs with Verilog HDL and Vivado

[@purplerb6378]

Thank you for giving us such amazing lectures !!!

[@jameslee6010]

Thank you my bro, amazing tutorial!

[@pradeeptirukkovalluri852]

Hello Vipin Kizheppatt, Thanks for the tutorial, just wanted to share one issue what I have faced while execution on board. During modeCOntrol block instantiation, for these inputs -- we gave valid_vote_1, valid_vote_2, valid_vote_3, valid_vote_4 But some how that didn't worked and I was not able to see results in mode=1 .candidate1_button_press(valid_vote_1), .candidate2_button_press(valid_vote_2), .candidate3_button_press(valid_vote_3), .candidate4_button_press(valid_vote_4), So I tried to replace those four inputs like shown below, and it worked for me 😊😊 .candidate1_button_press(button1), .candidate2_button_press(button2), .candidate3_button_press(button3), .candidate4_button_press(button4), Thanks for the support !!

[@rekhananaji9272]

excellent sir do more projects sir like this

[@kayitbilgileri]

Great tutorial! Thank you!

[@danushranganath9829]

Sir, I want to simulate the project as a timing diagram. So, do we need a test bench code for the same? If required, can you please help me out with the design of the test bench code and timing diagram.

[@engineeringstudies9828]

This tutorial is helpful. Can the counted vote be displayed in the oled display that how many votes have got each candidate....

[@hthrun]

Thank you very much! A couple questions: 1. 53:00 Since all four valid_vote signals are going into MC, could you have just ORed them inside the modeControl module and save an input? Would that have affected how it got synthesized? For example, does it save space to have less ports on modules if possible? 2. 59:45 If you just put that if else statement all in an if statement that checked the mode, would that have saved space in synthesis? Would that create fewer gates?

[@hippohop6715]

Very nice video sir !

[@uzairpatel3922]

Very informative video sir, can you please tell me which FPGA board is used in video

[@Jocjabes]

This was great. Thank you for your time. Why not use case statements rather than if ones?

[@Vipinkmenon]

In most cases if conditions and case statements will infer same hardware. Modern eda tools are very smart. But yes it is true that using case statements for mutually exclusive conditions are encouraged for optimization rather than if else which may generate unnecessary priority encoder. I am not aiming for optimal hdl styles in this tutorial. May be that could be another series.

[@jyothigayathriyellapu]

How we apply 100 MHz clock in vivado simulation?

[@shwetarajput7902]

Will this work for spartan 6 FPGA board?

[@RSP-zk8yb]

can we show output with out hardware ? if yes how?

[@eigenfield]

Zedboard vs zybo z7-20?

[@mallemoinagurudarpan2686]

i can get test bench code for this

[@ganapathivenkadesh8807]

Amazing

[@ritikasingh9219]

Thanks for the video Sir... But in one of the comments.. it's written 1sec/1ms =10^8... I think it should be 1 sec/10ns as the frequency is 100 MHz

[@Vipinkmenon]

Yes. It is a typo.

[@asramalik1027]

Thanks for the video sir can you explain how to find size of counter as in it 31 bit counter is used

[@physicsandtechnology8794]

can you pls explain difference between xilinx ide and vivado and why you are using vivado

[@Vipinkmenon]

Xilinx IDE you mean ISE?

[@physicsandtechnology8794]

@@Vipinkmenon yes sorry its ISE

[@Vipinkmenon]

ISE and other Xilinx tool chains (XPS, PlanAhead, ISIM) retired in 2014. From 2014 onwards the hardware design suite is Vivado. It integrates all functionalities of ISE, XPS, PlanAhead etc. and is much more powerful. Xilinx were using third party tools in the backend for synthesis (Simplify). The have totally redesigned it and now uses their on software. All latest FPGAs (7-series, Ultrascale, Ultrascale+) etc. are supported only in Vivado since they came after 2014. ISE you can still use for older generation FPGAs (Virtex 5,6 or Spartan)

[@physicsandtechnology8794]

@@Vipinkmenon so as of now I am using ISE for my verilog designing will it effect my learning

[@Vipinkmenon]

No. For learning FPGA design ISE is good enough.

[@ajayindhrajith313]

Sir Explained Well sir. How can we add some extra features like finger print sensor and how to interface it sir?

[@Vipinkmenon]

You can interface almost any sensor that you can interface with platforms like Arduino. Your sensor might have spi/i2c/UART interfaces. Will have to use PMOD connectors of the board to do it and will also have to write an application software running on the PS part of Zynq. There is a tutorial on interfacing esp module for enabling wifi in the playlist. You can check it

[@amanchoudhary0486]

Can someone provide source code

[@Rajeshhhhhhh]

Sir code please

[@kvkrcsetty6555]

What was the new concept exist here?

[@Vipinkmenon]

This is just for practising verilog