Difference Between Latch and Flip Flop | Latch and Flip Flop Difference | VLSI Interview Questions

[@Electronicspedia]

Please Like, Share and Subscribe to my channel kzbin.info/door/3mTACG8vPWsHQFMfxzeDZg

[@saithejsinghmanchikalapati5242]

Thank you for your explanation sir , please make a vedios on complete cdc for beginners and lint sir

[@Electronicspedia]

Hi Sai Thej, I have already covered basics of CDC, Please check out these videos, kzbin.info/www/bejne/j4SQfXuwl5mXoMk kzbin.info/www/bejne/nKjLXn5_iLymbcU kzbin.info/www/bejne/p3XRiIymZtN6b6s kzbin.info/www/bejne/pae0ZomPoaqWbtE Thanks.

[@naseemsultana7942]

Sir, at video 6:11, when enable signal second time becomes high and then low, the latch output should be also low, since enable becomes 0. why should it follow sig A, if En is 0. Please clarify. Thank you

[@Electronicspedia]

Hi, Latch is level triggered (either positive level or negative level). So, when there is an active level(enable), then it samples the new value of input (in this case SigA) , when enable is inactive that time it retains the previous output. This is the latch behaviour.

[@SauravKumar-kc4wg]

Sir, if latches are faster than ff then why we use ff in mostly place??

[@Electronicspedia]

Hi Saurav, Latches can result in glitches if we have the enable/data input signal not wide enough. That's the reason flip flops will be used mostly to avoid unnecessary glitches.

[@SauravKumar-kc4wg]

@@Electronicspedia okay thank you sir ...could you please upload videos on clk frequency div...like f/1.5,f/2.5.

[@Electronicspedia]

Sure Definitely will upload videos soon. Thank you for suggesting. 👍

[@Electronicspedia]

Sure Definitely will upload videos soon. Thank you for suggesting. 👍

[@shubhamkinhikar3250]

Can you please make a video on Ashynchronous fifo?

[@Electronicspedia]

Sure will cover it soon. 👍

[@akshitharavi3700]

As per your waveform diagram latch output is not depending on clock is it true?