Does Return Current Flow Under Signals? Watch these examples ...

[@mahoneytechnologies657]

Mr Robert Feranec your Videos are generating a lot of thinking in people's minds, Keep it up!

[@kacperbardecki3671]

1:30 to 1:50 blew my mind. Incredible when tech lets you see things you've been told to try to imagine for so long!!

[@hlavaatch]

Standing wave minima/maxima, sides of slit acting as a capacitor plates

[@RobertFeranec]

Thank you Jan

[@icestormfr]

Slit: also acting as a series inductor in GND path, breaking up the trasmission lines in two parts, with ohm&inductive coupling of traces where their return current overlaps (slit edge/plane connect)

[@engineer9750]

yeah I thought the same. The slit kinda acts as a capacitor.

[@Carlos-nm3ej]

I think the superposition of the wave. On higher frecuency the track work as transmision line so part of the wave was reflected and the wave will have min and max points.

[@wrekced]

@Robert I think that the nulls in the current on the boards are a product of the resonant frequencies of the individual traces and the inductance(s) and capacitance(s) between the traces, and between the traces and the ground plane. Those three sets of things mix together to produce the nulls and peaks in the currents on this board at various frequencies. Thanks for another interesting video!

[@rb8049]

If impedance matched at both ends, this does not occur.

[@johnnycernato4068]

I'd blame mostly the simulation itself for it's artefacts. The fact that the low-frequency results differ so much from the DC simulation suggests that the methodology is not very stable, at least not over the wide range of frequencies. I'm thinking hard of a way to experimentally verify some of these results... Maybe thermal imaging? Raster-scanning a Hall-Probe?

[@RobertFeranec]

I was also thinking, that maybe the way how AC simulation is calculated will not provide very accurate results for very low frequencies. But I am not sure, the best would be maybe talk to someone from Keysight who know how exactly the simulations are done.

[@sarowie]

thermal imaging is to slow and you would observe both current density and heat distribution effects. Note that using a high current pulse of DC current/low frequency would not work, as a pulse is by nature a higher frequency. Thermal imaging also has the weakness, that the warming up of the material increases the resistance, so by increasing the current to increase the contrast in temperature, you loose contrast by changes in resistance by thermal effects. Hall raster scanning sounds awesome, but I think the usable reliable dimensional resolution is limited.

[@RobertFeranec]

@@sarowie From my experience when making my previous videos with thermal camera, thermal imaging on GND plane would not probably work ... the heat spreads a lot on planes, unless you have super sensitive thermal camera, I would not expect much to see there. Here is the video (you can see, it was only visible when I used a grid): kzbin.info/www/bejne/goKVYXp4pNOFo6M.

[@johnyang799]

It's still 3khz. You really need to be 300hz and below to be actually low frequency. For AC to behave like DC, you probably need sub 10hz.

[@nikosant03]

Great great great video!!! I new about the returning path of high frequency signals, they actually follow the path of less inductance (and not the path of less resistance as in DC case) but I never have had the chance to simulate this and actually visualize this phenomenon. Thanks for your effort!!

[@RobertFeranec]

Thank you nikos

[@gudimetlakowshik3617]

Oh my god.....this point is always been in just theory but this is the first time I've witnessed...thanks a lot robert....!!

[@RobertFeranec]

Thank yo Gudimetla

[@nanobrad]

Some additional simulations that might be interesting: 1. Only one driving source. Visualize the current density in the other traces as frequency increases as I expect the energy is radiating to the other traces. 2. Only one serpentine trace. See how the solver works in the simpler situation and see what the resonant frequency of that single trace is 3. Run a crosstalk simulation that would indicate how much coupling you should expect with the geometry. As an aside, I think of the increasing frequency like a flooding river. At low frequency (i.e., low water level) the flow is easy to understand. As frequency increases (i.e., river begins to flood) you have more and more complicated paths for water to flow. In this case you have traces on the top side that can carry both forward and return current and capacitive coupling across the slot.

[@pamersiel]

The Finite Element Method is capable of creating many artifacts as well as completely wrong results. Try to play with grid density if the program allows it. If the result stops changing when the grid density increases, we usually get closer to the true result (but we can also get away from it).

[@nihar0689]

You see a change in input at low frequency which can introduce harmonics that make the simulation look different than DC. In case of the simulations being different at way higher frequency like the one where some parts of the tracks don't see any return current, I think that the return curent for that track is flowing through the adjacent track since it finds the impedance of that track to be lower which is a case of cross talk. This cross talk could be a result of inductive and capacitive coupling ( judging from that pdn graph u showed). I might be wrong here but just trying to make an estimate of whats going on.

[@RobertFeranec]

Thank you Nihar

[@re8et355]

I was thinking the same, also because there is a somewhat regular motion in the time-captured event following the frequency increase. So I double up with this comment.

[@NeuroMod]

These simulation videos have been very interesting, I would love to see more of these videos. I remember reading somewhere that Keysight was offering some long duration trials during the pandemia, but can't find the link. All of a sudden I felt the need to play with it.

[@RobertFeranec]

Thank you NeuroMod. I am planning to make more ...

[@haribabuk850]

That's amazing video, always your videos makes learn something new, Great job sir.

[@RobertFeranec]

Thank you Haribabu

[@ernierock8715]

I am a bit unclear about the setup, are the ports matched or are reflections possible? And how long are the traces? It looks like there are standing waves/transmission line effects at some points, with a strong influence from crosstalk (eg at 6:50 there are nulls in the current distribution, but they aren't all the same distance from their source), but I am too much of a noobie to say. With them spiralling around each other there is probably strong capacitive and inductive coupling between all lines. At 6:50 maybe we can imagine the rightmost spiral to be a circular inductor, with a magnetic field pointing into the page as per the right-hand rule. Then, we can imagine the U-bend on the left of this coil to be a similar coil with an opposite direction of current flow, and thus a magnetic field pointing out of the page. At the transition between these two coils, the magnetic fields will cancel, and there the current distribution is zero.

[@RobertFeranec]

Thank you ernierock PS: 1) no impedance matching (I am not sure if the simulation will include reflections ... a good question). 2) SIG1 = 255mm (100073mils), SIG2 = 186mm (7331mils), SIG3 = 141mm (5576mils)

[@punitjain8746]

Thanks for this. at 15:06, the nulls seem to be at equal lengths from the source ports.

[@uccoskun]

@@RobertFeranec and at 300MHz wavelength is around 70mm. I think you just see standing waves as others mention.

[@doktortronikelektronikaszk4070]

I think its a skin effect that leads to increased apparent resistance under the traces thus the current, assumed constant for all simulations, takes more space on ground plane and keeps the voltage drop almost the same (i.e. apparent resistance increased->ground plane voltage close to traces wants to increased->more cooper conducts to prevent this voltage increse). For microstrip a good current density approximation under the trace is around 5x trace tickness.

[@AhmedHan]

13:00 Could it be because the loops act as current transformer and reduce each others current? And maybe the reason why the outmost track dominates others is simply because it has the most inductance because it has the largest radius.

[@arashcrouse2]

This video is very interesting. I think the effect at high frequencies is due to dielectric thickness. It is perhaps a thick one!

[@YavuzAyrak]

Hi Robert, Firstly, It is a very good demonstration and you would refer important issues in your videos. In my opinion, at low frequencies on your board signal traces track low impedance as at high frequencies. As long as frequency is ascend, low impedance is coming up to onto signal traces. As a result red regions are overlapping with signal traces. However I have no exact idea for what happen at very high frequencies. Maybe, it is happen because of EMI effects.

[@RobertFeranec]

Thank you Yavuz

[@dflyfpv8765]

10:34 One thing i know is that on a wire current flows better on the outside than through the inner core (which is an opposite behavior of what water would do on a pipe). Electrons tend to interfere with each other in the center and so decelerate their flow. That's maybe why the track that is close to the outer wall is the one getting most of the back current flow.

[@icestormfr]

For high frequencies: ---------------------------------- From the impedance graph it looks like a resonance. What was your AC settings (you showed the DC settings in the video)? C an you set phase difference to the sources? Can you set the load to a impedance value corresponding to the characteristic impedance of the microstrip? If you have a microstrip on a 2-Layer PCB (h=1.6mm, w=0.2mm) @100 MHz, a trace length of 225mm corresponds of a electrical wavelength around lambda/8 (30...45°). So if the sources and loads are not matched to the trace, standing wave patterns will arise. Also, due to inductive coupling the three microstrip lines could create a coupled resonator. With the break in the reference plane, the return path introduces several differences: * the effective trace/signal length increases => standing wave resonances in the microstrip occur at lower frequencies * the coupling of the traces/microstrip increases strongly as their return path conductor overlaps * the slot creates an antenna...but I don't think that you'd see that in the AC analysis as the PCB is not in the farfield of itself ======================================================================= For low frequencies: ---------------------------------- The AC simulator is probably not intended for that low frequencies. From the "Advanced Design System 2016 Update Release Notes", "Signal Integrity/Power Integrity (SIPro/PIPro) ": "Improved behavior for low frequencies: automatic frequency plan option uses 20 kHz as the lowest calculated frequency" So, 0.020 MHz should be a lower limit Source: edadownload.software.keysight.com/eedl/ads/2016_01/updates/Update1_3/pdf/ADS_2016_Update_Release_Notes.pdf

[@RobertFeranec]

Thank you very much Ice Storm. PS: I have not seen any special AC settings. I am not exactly sure how the frequencies are actually tested. Only what I set was 1.5V for amplitude (I believe). And you are right .. it would be interesting to play with impedance matching, that could be interesting to see.

[@icestormfr]

@@RobertFeranec Are there settings in "Mulit excitation" regarding phase? Otherwise, I guess it's not intended/supported by ADS (at least for PIPro), or a very hidden setting. Although I've seen AC source definitions (used as sinks) in ADS schematics with phase (polar(amp,phase)): www.keysight.com/us/en/assets/7018-05074/data-sheets/5992-1291.pdf www.keysight.com/upload/cmc_upload/All/5_Power_Integrity_Ecosystem.pdf Regarding transmission line resonances: www.allaboutcircuits.com/textbook/alternating-current/chpt-14/standing-waves-and-resonance/ I guess the AC simulation uses the power sinks as "AC current sources" (load current) with your power sources acting as "R-L loads" (with DC-voltage that acts as short in AC simulation). As your sources have zero impedance (R=0, L=0) you have the "shorted transmission line" case. 1) At quarter wavelength the first resonance peak occurs: * at the end of the line (at your power sources): voltage is zero and current maximal * at the start of the line (at your power sink): voltage is maximal and current is zero => resonance peak PDN impedance (or infinite impedance in case of no losses) => your 100/170/200 MHz peaks 2) At half wavelength the first anti-resonance peak occurs: * at the end of the line (at your power sources): voltage is maximal and current zero * at the start of the line (at your power sink): voltage is zero and current is maximal => anti-resonance peak PDN impedance (or zero impedance in case of no losses) => your 200/340/400 MHz notches (only first one was inside your simulation range) I tried to reproduce a simplified simulation in LTSpice. It looked similar, just shifted frequencies by factor 1.5 (~160/220/290 MHz & 320/440/580 MHz). Assumptions: stackup/microstrip config: 1.6mm thick, two layer, 4.8 dielec., 0.1mm trace width PCB size: 100x100mm approx. length of traces: 150, 200, 270 mm net list: V1 N001 0 1.2V AC 0 0 Rser=0 Cpar=0 I1 V1 0 0 AC 1 0 load V2 N003 0 1.2V AC 0 0 Rser=0 Cpar=0 I2 V2 0 0 AC 1 0 load V3 N002 0 1.2V AC 0 0 Rser=0 Cpar=0 I3 V3 0 0 AC 1 0 load O1 N001 0 V1 0 LTRA1 O2 N003 0 V2 0 LTRA2 O3 N002 0 V3 0 LTRA3 .ac dec 300 20k 600MEG .MODEL LTRA1 LTRA(R=4.9 L=883n C=37p LEN={0.270 * FAC}) .MODEL LTRA2 LTRA(R=4.9 L=883n C=37p LEN={0.200 * FAC}) .MODEL LTRA3 LTRA(R=4.9 L=883n C=37p LEN={0.150 * FAC}) .param FAC=1 .backanno .end

[@guillep2k]

@@icestormfr You wouldn't believe me but I've seen a problem like this and a response like yours in meme site 9gag a couple of years ago!

[@icestormfr]

@@guillep2k 😳😳😳😳

[@RobertFeranec]

@@icestormfr Thank you. Nice! PS: I asked Keysight for more support to help with these simulations, so I hope I will learn more about how the simulation works and what kind of settings I could also try to adjust.

[@jb9282]

TC 2:00 - Question AC Current : this static time picture of current ( a moment record of 400Hz ) ??? Or really dynamic flow ? 😉😎 -My point of view is - you looks to a static time stamp ( non dynamic ) and you don’t know , are you on 1/4 wavelength or a 1/2 position ? 😀 Of course currents amount is on 1/4 different then on 1/2.

[@physics_thug]

Yes, a complex magnitude would be more revealing, or a short clip in time to see the nulls traveling with the wave

[@mahoneytechnologies657]

Resonance Frequencies! and I would look at where the peeks and vallies are along the trace as the frequency changes and with the corresponding wave lengths change, and where the at the opposing signal applitudes are at along opposing traces in relation to each other to take into account their influence on the opposing wave.

[@Cracked1ce]

As you go higher in frequency (Ghz), the track length is playing a bigger role. if you think about the wave traveling forward, you can also think about the return current traveling backwards in the plane. The falling edge behind the rising edge is in a sense, canceling out the return current. For around the 300 Mhz areas i think the standing wave theory that was presented in the earlier comments is the cause of those points with low return current. I would be interested to see a simulation with differential traces passing over a split in the ground plane. as well as having the ground planes on either side disconnected. This would provide some valuable insight on differential data signals coming out of an ADC or into a DAC with the analog having a separate ground plane

[@TrickyNekro]

I would like to see the differences with various PCB thicknesses!

[@electron_]

There are three factors which must be considered: 1. VSWR due to impedance matching 2. Skin effects on higher frequency are forcing the current to pass widely until capacitance factor from the bottom ancts as lpf. 3. Crosstalk due to nearby lines George

[@RobertFeranec]

Thank you djordje2404

[@cirdiam1800]

I think the gaps at certain frequencies is due to reflection of the signal back along the trace toward the source causing destructive interference in certain places.

[@mahoneytechnologies657]

it would be an interesting to see the simulation of the signal line with a little oversized ground line directly beneith the signal line, with and without a general Ground Plain surrounding the ground trace, with various gaps!

[@tuskiomisham]

This has been said but the current is also a function of the density of the charge on the plate.

[@-Oleg1]

Hello. I guess the current difference between tracks is made by 1. Interference between them (to change vary the phase between them) 2. Different inductance (because of different radius of curveture) 3. Different positions compared to gap bridge( bacground conductor on top). And the second thing. The gap behaves as a conductor and a capacitor in paralel. So if devide gap on little horisontal straps, they will behave as vertical conductors and horisontal capacitors. So all that gap is like paralel capacitors connected thru serial resistance

[@-Oleg1]

The back current flows under neighboring conductor because of interference between currents of this conductors. Try to visualise difference between back currents in dependance of current phase in conductors.

[@-Oleg1]

Decreasing frequency had to illiminate difference between ac/dc simulations. Seems like some simulation or imaging error

[@ahbushnell1]

The DC problem with the slot looks like there is a meshing problem. Is the mesh too coase?

[@hugoboyce9648]

Thought the same

[@32bits-of-a-bus59]

It occured to me too. Just look at the current map near the connectors -- there is no reason for such sharp-bordered triangular areas of high current.

[@RobertFeranec]

I will ask Keysight if there are some settings what I could change.

[@sepphuber7434]

As a starting point you should use matched impedances and then go from there (50 ohm source impedance, 50 ohm transmission line, 50 ohm load impedance).

[@RobertFeranec]

I will try that ...

[@navu2468]

Nice presentation RF

[@RobertFeranec]

Thank you Navaneethraj

[@myhobbies5965]

Love your curiosity.

[@aniketghosh8812]

The simulation results are weird at very high and low frequencies. At low frequencies, it should have matched the Dc Analysis. But for higher frequencies maybe the skin effect is playing a major role. I am not sure just a wild guess. But would love to see a video clarifying these weird results.

[@thear1s]

My guess for low frequencies is that they're using a different simulation model than for DC, it's very possible that the results aren't close to reality under a certain frequency.

[@vladlv2]

the closer you get to wawelengh probably more probable starting to see points where waves are "standing" in fact it could be nice to see how sharp corners affect RF but probably you will need to get more serious simulator, like ADS it is proven that below 1ghz it is not affecting much, above 1gh to 10ghz still mininal effect for sharp corner.

[@sarowie]

before changing the software, it would make sense to check the setup of this simulation software. If the mesh grid is too course for board size and signal frequency or current densities get out of range, then strange artefacts will happen.

[@sarowie]

above 1 MHz: could that be skin effect? It is hard to guess if the dimensions are not explicitly listed. Skin effect is even relevant at 50 Hz powerline transmission level. Or capacitve coupling between signal traces?

[@engineer9750]

skin effect depends on the current strength

[@ATauheed]

What software is that you are using for the simulation? Really would love to learn it.

[@RobertFeranec]

I use ADS from Keysight www.keysight.com/en/pc-1375582/advanced-design-system-ads-simulation-elements?cc=SK&lc=eng

[@williefleete]

interesting effects. I would say the DC sim would be different to the AC because even though it is a low frequency it will still be switching back and forth. At those higher frequencies and with the ground split it is possibly acting like an LC filter, the narrow point in the ground plane acting as an inductor, and the traces and what is left of the ground plane each side acting as (distributed) capacitors, it is possibly attenuating the signals at certain frequencies

[@RobertFeranec]

Thank you William PS: I have similar theories. Let's see what other people will write.

[@fpgaguy]

first I would also play with meshing options and take a look at what you get with ansys, try a single trace also. I had no idea the slot would form hot spots extending so far along from the constriction along the edge at AC. A thought of applying f @ 10W and observing thermally comes to mind to avoid any probe effects - but I'm probably wrong on that.

[@garimagarg2739]

This is really interesting video.

[@RobertFeranec]

Thank you Garima

[@siddharth9678]

Nice video..Very much informative...👍👍

[@RobertFeranec]

Thank you Siddharth

[@ricolauersdorf687]

-Will the current also return under the track, if there is a gnd track provided next to the "pulsed" one on same layer and both are a straight lines or lets say the top layer is also a filled polygon? -In terms of emv, does it make sense, to route positive and negative connection in differential style(?), or in the intrinsic way, it travels as you have simulated? Will the received noise of an analog component somewhere else on the PCB be less, if both current paths are close to each other and both somehow seperated from the gnd plane?

[@mcconkeyb]

At a high enough frequency the gap will almost disappear as the signal will transition from flowing in the copper to flowing through the air as either a near field RF signal or at super high frequencies, much higher than what you were showing, it will transition to a far field RF signal. The real question is whether the simulator is smart enough to get all of these transitions correct. This "strange" behavior is how distributed circuit elements and other fancy RF filters and antennas are created. Once again the real question is on the ability of the simulation software to get all of this correct. In the old days of RF design if you knew how to do this, you were a master of the black magic of circuit board RF design. :-)

[@RobertFeranec]

Thank you Brian. Maybe it would be interesting to ask at Keysight to explain what the software is considering ...

[@liquidcable]

I'm pretty sure it's this. The current / energy is flowing through air via RF just like an antenna and just like the energy in a PCB trace is traveling in the dielectric and not the copper. High frequency of course, not DC.

[@meetpatel6049]

Thanks Robert for this simulation, Did you got answer why there was discontinuity of return current at high frequency(300Mhz)?

[@asghar5152]

Hi Robert for pdn analyses which software should i use ? I want to check my pcb impedance wrt frequencies, there temperature rating on the basis of high current track and decoupling capacitance etc

[@torique6250]

Hi, thanks for the great video! What was the simulation CAD name?

[@sinaaghli]

on 13:00 it could be because of reflections. When signal's return path cuts of like that you are gonna have a reflection which could be high enough to cancel the original signal. hence no current would show up on the return path. this topic is well discussed in chapter 8 of www.amazon.com/Signal-Power-Integrity-Simplified-Prentice/dp/013451341X

[@RobertFeranec]

Thank you sina

[@mikitashary5552]

Hi, can you make a video with more detail info about how you import this layout to ADS from Altium and how you`ve got this result.

[@RobertFeranec]

I may go back to this topic in future. PS: I speak about import from Altium and ADS settings for simulations in some of my previous videos e.g. here: kzbin.info/www/bejne/a2epp4SOa5h4l5I

[@tsusec]

If the theory about second board is correct about LC filter acting properties, the missing currents at certain frequencies would indicate parallel resonance of that filter... I didn't check at which frequencies that happened, but that may be the case. Because max trace length with return path is below 5*(wave length) i guess.

[@RobertFeranec]

Thank you Matija

[@shnuk007]

Thank you very much! This is very intersting. If you could, please add capacitors near each trace so it will connect gnd planes via the capacitors near the traces. It is very intresting what will be the results. Thanks

[@RobertFeranec]

Thank you Alex. This may be interesting for you (it has capacitors): kzbin.info/www/bejne/rKvUi6BofquhbLs

[@mahoneytechnologies657]

It would be neat if there was a plastic film product with a material that shows a visible change in relation to the frequency and/or raw signal amplitude and direction, there is a product like this for visualizing steady magnetic fields I have seen. Just think if one could just lay such a plastic sheet across your PC Poard and see information like this! It would be in real Time!

[@XxfieryfirexX]

Thank you robert for the Video. What exactly is the return path flow simulation used for ? is it for DC-DC power supplies? or high frequency communication like SPI,etc? also how to make optimizations based on simulations, do we just see do the simulation, with no cuts? or do we make the cuts in the plane for a reason? im not sure whats the disadvantages. please explain

[@Su67377s]

U r making very good videos. keep it up!!!👍👍👍

[@RobertFeranec]

Thank you very much Sumit

[@shnuk007]

8:30 - 8:40 - Do you have an option to look in a cross section view? Maybe this happens due to skin effect. Maybe the current spreads to the sides instead of flow thru the entire cross section of the GND plan?

[@carnright]

Amazing! Maybe a Hilbert curve next?

[@NEEC1]

Hi. Its hard to see why there would be any difference at all from DC to 400Hz. They should be identical. If not, then its most likely due to simulator artefacts. You should only really start seeing differences when you get into RF frequencies roughly above 10Mhz and beyond. After that, using PCB with thin copper tracks, things will start to change. The gap may start working as a capacitor and may start conducting across it. Also, the capacitance from top to bottom tracks start to conduct through the board. At even higher frequencies, like 400Mhz, you may see currents in the track actually stop then start again on the same track. Thats because of standing waves beginning to form. RF radio designers are very aware of these problems and designs have to include very short tracks and good large area earth returns to reduce losses.

[@RobertFeranec]

Thank you

[@triffid0hunter]

Did you tell your simulator that all the input ground pins are linked externally? Perhaps it's simulating one ground pin carrying a lot more current than the others due to the board geometry - in which case forcing it to simulate isolated supplies and loads should help get the results you're expecting…

[@БезумныйСерж]

Robert good evening, great videos you shoot,I myself am a novice circuit engineer and do not fully understand the process of creating an integrated library,if it is not difficult for You, please shoot a video about creating an integrated library, I will Be very grateful to you!!!!!

[@punitjain8746]

He already has videos about how to make a library. If he hasn't included, you can create an integrated library by right-clicking on the LibPkg project in altium and select "Compile...." it'll make an integrated library in the Outputs folder.

[@RobertFeranec]

@@punitjain8746 Thank you

[@RobertFeranec]

Thank you Sergej. PS: As Punit pointed out, there is nothing very special about integrated library.

[@mdchethan]

At high frequencies, the skin effect becomes more prominent and which makes the current to flow through only the outer layer of a conductor.

[@p_mouse8676]

My thoughts. It is still simulation. Which means there is always a possibility that the simulation model isn't totally accurate as well. As for the dips in current. Aren't those just resonances? Btw, current doesn't go with the shortest path but with the lowest impedance!!!

[@RobertFeranec]

Thank you P_Mouse

[@hiteshjangra81]

one thing i want to ask in which software you simulate your tracks or PCB and is there any chance we can simulate in Fusion 360 or Eagle?

[@hugoboyce9648]

Interestng video!

[@RobertFeranec]

Thank you Hugo

[@Hadi-zw9mb]

I am not sure which simulator did you use. But it is better to utilize Momentum Microwave for lower frequency rather than FEM.

[@MakerBrothers]

How long would it take for the return current to go from initially returning under the signal traces to taking the path of least resistance if DC switched on

[@madhum8046]

Nice video! .. Very useful. :)

[@RobertFeranec]

Thank you Madhu

[@abdelkareemsalem8697]

What is the program used for simulation?!

[@amjadrifqi2464]

What happens if you have a ground copper pour on the top layer. in two layer PCB the ground plane on bottom layer might be discontineous because it has some routing tracks

[@knikhil91]

Hi Robert, Firstly thanks for the nice demonstration of the high frequency currents, I'm also curious to know more about the cause of this... Bydaway, you mentioned in some of the comments that you had used ADS from Keysight for the Electric Field simulation of altium layout, Is there any tutorial on how to use ADS software to implement this DC/AC analysis for the Altium Layout?? That would be very much helpful !!

[@RobertFeranec]

Thank you Nikhil. PS: I think, in this video I went through the process of importing Altium into ADS: kzbin.info/www/bejne/a2epp4SOa5h4l5I

[@knikhil91]

Thank you, @@RobertFeranec

[@guillep2k]

Sinks are set up for a fixed current, so I guess because the top track is longer (i.e. more resistance), more power is dissipated in the track to achieve the same current at the output port... maybe? I would like you to plot a sample of the input signal: is it sinusoidal? square wave? (is it irrelevant for that kind of analysis, perhaps?)

[@RobertFeranec]

I will ask these questions to Keysight

[@Galeere2]

I don't have any experience in simulation, but is this able to simulate Couping in EM Fields? Could some of the artefacts come from coupling between tracks and destructive interference? Can you simulate two antennae, one sender with an ac current source and one receiver with a closed loop or resistor load? To see if currents are transmitted

[@RobertFeranec]

If Keysight will help me with 3D field simulations, I will do that.

[@ahbushnell1]

On the slotted board the skinny part should have very high current density but it seems similar to the other parts????

[@RobertFeranec]

I am not sure if you mean this, but it looks like when I adjusted the Range, it is visible at 12:25

[@ahbushnell1]

@@RobertFeranec i posted before the end. :< I think the mesh size should be adjusted. Great tool.

[@sorarami5770]

I am not sure what about the simulation software you have used, but for ansys q3d, it uses FEM for the dc solver and BEM for the ac solver. Maybe this can be one reason for the difference between ac and dc results.

[@nealcaffrey7888]

Which kind of simulation software did you use in this tutorial? Thank you

[@aDaWaN]

Keysight ADS SI Pro

[@mehdikhalfallah3056]

nice video, as always :)

[@RobertFeranec]

Thank you Mehdi

[@nenharma82]

Wait, you learn about electronics in elementary school? 😜 great video! Always wanted to see this, too!

[@RobertFeranec]

:D Thank you nenharma82

[@annacersongor8553]

Standing waves propagating in an unmatched impedance ttansmission line causing Incident propagating waves to interfer with reflected ones.

[@harryw489]

Thank you sir, very inspiring video. I see you are using Altium in this video, what is the flow from Altium to ADS, ODB++? Also ADS is expensive, is there any free or cheaper field solver recommended?

[@RobertFeranec]

Thank you Harry. PS: yes, I used ODB++ to transfer the board into ADS. I have only played with ADS (they provided me the license), I have not tried any other tools.

[@CallistoPili]

@@RobertFeranec there are some temptatives in progress to integrate KiCAD with OpenEMS/Paraview, using Hyperlynx format or other tools like Pcbmodelgen as frontend but still primitive atm

[@sarowie]

could you please enable automatic range? I assume the current density does get pretty large, once the current flow gets very localized and gets out of range. One Simple example of why I think of a range problem: With the cut in the board: why do I not see an increase in current density, where there should be copper shared by the signals?

[@RobertFeranec]

I intentionally disabled automatic range as then it doesn't show well absolute and comparable results with images for different frequencies. But, I will play it.

[@bejancornel5224]

Hello, Robert Feranec, Can you make a video or videos in which you explain the ADS (SiPro and PiPro) software for simulating PCB step by step? I am interested to see the process, step by step, of importing files in ADS (SiPro and PiPro), which are the proprieties I need to configure to analyze a PCB in terms of signal and power integrity, thermal simulation, and so on. Thank you.

[@RobertFeranec]

Hello Bejan. I have done simple setup for DC and also explained simple AC setup in my previous videos about ADS. Have a look for example here: kzbin.info/www/bejne/a2epp4SOa5h4l5I PS: For more complex simulation, I will still need someone from Keysight to help me.

[@bgdwiepp]

I think why the current starts to spread out above 1Mhz is because of skin depth, then as frequency increases more and more you start to see the effect of standing waves having maxima and minima.

[@bgdwiepp]

i think at VERY high frequency the current is directly under the traces, but so tightly it is hard to see, it is directly under the traces and so tightly under them because the return current cancels out the inductance, and that makes such a big difference compared to the other factors.

[@jeraneurism3998]

The slit could be characterized as an open-ended slot antenna.

[@rogerfurer2273]

Above 1MHz seems related to the impedance somehow. I seem to remember an old Analog Devices App Note that suggested having ground tracks directly underneath each signal track and connecting them to a single star ground point at one end of the board. I recently searched for that note (on behalf of somebody else) but was unable to find it. I'd be very interested to see what (if any) difference it would make. (To have individual return paths below each signal path. These would be in addition to the ground plane.) If/when you get a chance.

[@gn_ghost4757]

I think this is what you were looking for: www.analog.com/en/education/education-library/linear-circuit-design-handbook.html (Chapter 12: Printed Circuit Board (PCB) Design Issues)

[@rogerfurer2273]

@@gn_ghost4757 Thanks, but no, it is not the document I remember. What I remember was a single specific app note and this would have been around 2010 (plus or minus a couple years). I recall it as discussing VHF return paths under the signal trace, using a separated ground trace. My memory functions are glitchy these days, so I could be mistaken, but I believe this was before AD acquired Linear Devices (if that helps).

[@mahoneytechnologies657]

What is the simulation Program you are using? This way more interesting than any computer game, Will this is computer games for Technicians, Engineers, and all those interested in Technology!

[@stefanosavio7151]

Hi, any idea on how to have this result on ansys?

[@jrh1856]

I think that you could get a better understanding if you separe these tracks and make them straight.

[@hisham1269]

Yiyy, this simulation stuff is cool, what software is this?

[@flussoincrociato]

what software are you using to simulate return currents?

[@RobertFeranec]

I use ADS from Keysight www.keysight.com/en/pc-1375582/advanced-design-system-ads-simulation-elements?cc=SK&lc=eng

[@flussoincrociato]

​@@RobertFeranec thank you very much, if I buy W2200BP + W2360EP + W2359EP it is enough? Will I be able to perform the simulation you made?

[@RobertFeranec]

@@flussoincrociato I do not really know. Keysight provided me a license (I am not sure exactly which one) so I could make these videos. The best would be talk to someone from Keysight and ask them.

[@Ncky]

This is unrelated question but what to do when i need more than 10uF input capacitance on usb device side? 28pins have over 100uF on usb input vbus. What should i do? Is it really nesecarry to have under 10uF total capacitance or 50-100uF can be accepted to?

[@RobertFeranec]

The main reason why I used 100uF is to keep stable 5V even if a long cable is used and when board has some peaks and when it needs more power (simply to say, bigger capacitor will help to deliver extra power longer when needed). What you may want to consider is, what is your device current consumption and how it is usually connect (e.g. through cable or directly to port)? So, your device may work perfectly fine with all the kind of capacitors - but more power it needs, maybe bigger capacitor you may want to use. If you use a big capacitor for lower power device, it is ok ... just it may be unnecessary expensive (bigger capacitors are often more expensive).

[@Ncky]

@@RobertFeranec well i wanted to add 47uF but when i connect 47uF to my pc it resets the internal hub(usb disconnect sound)

[@RobertFeranec]

@@Ncky this may happen - it means the hub is not designed properly or it is not powered from external power supply and you already have other devices connected there. Basically what happens, when the 47uF is charging, it will cause voltage drop in the hub as the hub is not able to keep the voltage stable - that is my guess. Try different device e.g. PC or different hub to see if you will see the same problem.

[@Ncky]

@@RobertFeranec same problem on 2 other laptops too and on one pc(asus cross hair hero 6). The usb spec says that usb device must not exceed 10uF input capacitance. Which is correct. Internal Hub does not reset when i connect 10uF or 22uF cap. Anything over 22uF resets it. I have designed a circuit that has around 8uF on the vbus directly and the rest is behind voltage regulators. I dont know does the capacitance behind voltage regulators count as vbus input capacitance.

[@RobertFeranec]

@@Ncky Then I would go for 10uF PS: Also it may depend on what kind of capacitor you are using (electrolytic, aluminium, ceramic, ...)

[@AndrewJones-tj6et]

You are right to be suspicious of these simulations. They can so often trip one up :-) Got to carefully watch how the mesh is created, how the ports are defined as well as material definitions for tracks, ground plane, dielectric and enclosure. Looks like you are using FEM in ADS, I have used Momentum in the past. I would try to make a simple layout single trace, meandering single track to see what happens. Also use different ways of injecting and output of signals (ie. internal or edge ports).

[@RobertFeranec]

Thank you Andrew. Let me know what kind of results you will get.

[@AndrewJones-tj6et]

Sorry Robert, I do not have access to ADS these days as its very expensive as an individual for a license. I mostly surf the open source world now :-)

[@Chris_Grossman]

There are multiple effects that may influence the simulation, The finite element grid selection is both structure and frequency dependent. You have not shown your grid, it is key to the results, thus it is difficult to say what is happening. The multiple current paths couple with both capacitance and mutual inductance. You should start with a single path and then add the cut. The results should be very close for very low frequency and DC. The fact that they are not casts doubt on the entire exercise. Until you work that out I would not believe any of your results. What EM simulator are you using? How did you choose the grid?

[@RobertFeranec]

Thank you Chris. When you say Grid, what do you mean? The setup is super simple, I am using ADS.

[@Chris_Grossman]

@@RobertFeranec EM simulators use a grid to approximate what is happening. (See FEMM Finite Element Method Magnetics for an example). The grid is needed to approximate what is in fact a continuous phenomena. The art to such simulations is appropriate choice of the grid. It needs to be fine where things are changing in short distances, but can be wider away. The choice of grid point position and density controls both simulation time and accuracy. Too fine a grid density can cause round off errors. Too coarse a grid point selection will miss necessary fine details. ADS works ok for simple RF transmission line structures for which it has decent models. For anything besides simple transmission line structures we use HFSS.

[@RobertFeranec]

@@Chris_Grossman Thank you Chris. I will ask about this when I will be talking to Keysight

[@pranit9668]

can you please do a video about parasitic extraction (loop inductance, capacitance) using FEA of pcb?

[@asaadmakhalfih4199]

Intersteing! What's that software you use for simulation?

[@RobertFeranec]

Thank you Asaad. I use ADS from Keysight www.keysight.com/en/pc-1375582/advanced-design-system-ads-simulation-elements?cc=SK&lc=eng

[@Parsa1382-f8v]

did anybody find out why the current is missing in the part that the pcb had a big cutout in high frequencies?my idea is that the current closes itself in the air, becuase the maxwell rules forces it to form a closed loop.

[@electricspark7887]

Sir , Please make flexible PCB video

[@crimpers5543]

One of the reasons why I hate simulations. Results can be complete bupkis unless you tweak some magic knobs in the software's models and assumptions.

[@MrJetra]

It is a simulation. I don't know the tool, but from Spice I know that the result isn't better than the setup. Can there be something in the setup or in the sim itself that causes these "strange" results?

[@bladan83]

could be a limitation of simulator?

[@deweywsu]

Ah, so this is RFPro by Keysight. Looks expensive. Does anyone know of a free and/or open source alternative for electronics that can handle this kind of simulation?

[@RobertFeranec]

Yes, it is ADS from Keysight.

[@dhaneshchoudhary8906]

Above 1 mhz may be inmpeadence of air is 377 ohm so that y it's flowing from air

[@therandomchannel9226]

can u do the same simulation with a complete polygon as a GND plane (return path) and post a video

[@RobertFeranec]

Omair, I am not sure what you mean.

[@therandomchannel9226]

@@RobertFeranec as I see, you are using return path on bottom layer, which is a trace. I asked you if you can make bottom layer as polygon and use it as a return path. And observe the difference

[@RobertFeranec]

@@therandomchannel9226 Bottom layer is solid GND plane (polygon).

[@ABaumstumpf]

The simulation-method seems very unstable, not suited for low frequencies and very sensitive to the grid-size. Very likely the "missing" current is an artefact as a result of the grid-size and frequency: If the grid is coarse and the effect-ranges just line up with the grid then the result can be totally wrong. Just imagine it like this: At the left is the input, a thin trace on the topside going in zick-zack to the right where it is connected to the ground plane, but just 1point in between for the simulation. If the frequency and distance match up then the simulation might get near 100% capacities coupling between the left and the right. Decent simulations take a looooong time.