DVD - Lecture 5: Timing (STA)

[@tantuz1128]

This is by far the best explanation of STA I have seen.

[@AdiTeman]

Thank you so much for the kind words!

[@wlcheng]

Thank you so much for this wonderful introduction, Dr. Adam Teman. I wish I had a professor like you when I studied VLSI at first place.

[@AdiTeman]

Thank you for the kind words!

[@amangupta7535]

This is the best learning series I have even been through . Very well documented and it summarizes in depth detail about actual flow being followed in any industry . Thanks for the amazing lecture series !

[@AdiTeman]

Thanks so much for the amazing feedback.

[@supratimsaha3783]

I just discovered it. Hoping it will help add some knowledge.

[@LapinFou14]

I just discovered your videos. As a beginner in Physical design, it definitely made my day. So much clear and well explained information. A big thanks to you.

[@AdiTeman]

Enjoy!

[@socialogic9777]

Sir you are great! I started VLSI with a lot of enthusiasm, which was all lost when I started taking synthesis classes, I knew it wasn't as complex as it is being taught to me(Seemed like the first time I read quantum mechanics). I was aware of your lectures, and this playlist rejuvenated my passion in VLSI. Thanks a lot

[@AdiTeman]

I'm so excited to hear that!

[@dontevenwasteaday8983]

As a backend engineer from Cadence, I would say it is a very good lecture series. All of the fundamental but important concepts/topics are well domesticated. One thing make it stand out from other similar youtube channels is your new fashion: like MMMC is discussed here, which is rarely found from old school bookie(at least it was when I was in school). I noticed you had a non-English version of signoff video, hope you have it translated soon! Don't miss the last piece of your great work man!

[@AdiTeman]

Thanks so much for the kind words. I do, in fact, plan to record the signoff video in English. I just ran out of time when making these recordings last year, but it is on my todo list.

[@workthamngan9407]

You covered everything for a person to know about STA! Amazing sharing once again!

[@AdiTeman]

Thank you for the kind words! (But as a side note, there is a lot more to know about STA. I discuss some of it in the later lectures, but there are things that are emerging every day and with each new technology. A good place to find out more is the documentation of the timing tools, such as the PrimeTime user's manual).

[@workthamngan9407]

​@@AdiTeman That's totally true, you are missing on the pessimism(extra margin) part, RC extraction and final timing sign off both pnr and tempus/primetime in this video. In fact, you did mentioned in the video that you will cover that in the later stage. You are truly a meticulous person to state every single thing without missing any information. Overall, you covered everything which invoke "init_mmc" command in the Innovus. This is a wrapper of all the timing inputs inside there. Well, I am happy to go through the STA part in this video and did resonated well on every inch of the knowledge. cheers. :)

[@vboss1728]

The best video on STA I have seen so far. Awesome professor. Thanks a lot 🙏 100000 X 👍for this video. Will go through all your videos.

[@AdiTeman]

Wow, thanks

[@sudharsankannan6169]

Omg!!I can't thank u enough for this amazing lecture sir💯🙌🏻Hands down one of the best

[@AdiTeman]

Thanks!

[@iliachakarov7285]

These lectures are really well done!!

[@AdiTeman]

Thanks!

[@bharathsridhar8965]

This is precious....!! U r doing a great job...very useful material!! Thank you very much!!

[@AdiTeman]

Thanks so much for your kind words!

[@bharathsridhar8965]

Hi sir. Thanks again for all these wonderful lectures in digital VLSI design. Taking this lecture on timing analysis as reference we were trying to perform static timing analysis for a digital circuit using cadence tempus we are stuck at a point where we have timing violations and don't know how to correct it.could you please help us or suggest any reference materials as such. If you can provide your email ID it would be of great help and I can explain it more elaborately in a mail. thanks.

[@msaideroglu]

As a new graduate who has just started to work in the industry, especially this video and series are really useful for us. Thank you for your efforts. These kind of videos especially in digital VLSI area are very rare on net. Actually if an assistant or an experienced person could provide some practical tutorial videos such as ASIC design flow with industrial tools or design metologies or example design projects for educational purposes, it would be the best help for people.

[@AdiTeman]

Thanks for the kind words. I may, in the future, upload some practical tutorials, but I need to first make sure that I have the proper permission from the tool vendors and technology providers to do so.

[@StayInBliss]

respect you for sharing knowlwdge with all of us

[@AdiTeman]

Thank you!

[@nikitak3605]

thanku thanku thanku for such amazing lecture.helped me alottt.no words.hats offf :) looking forward for more videos on physical design..thanks again ..love from India ♥️

[@AdiTeman]

Most welcome 😊

[@DSPY1009]

Hi professor, this series is boon for VLSI aspirant. This is amazing series. And I learnt concept which I have used during my actual project. Thanks for such amazing series. Can u please make video , how AI/ML will change backend design work? Thanks in advance

[@AdiTeman]

Thanks for your comment! I do not yet know enough about backend with AI to teach about it, though this is truly something I have been interested in for a long time. I hope to learn more about it soon and then, of course, make a lecture!

[@isaackumba2688]

Thank you so much Sir , Its very helpfull 🙏🏻

[@AdiTeman]

You're very welcome

[@anandmodi6948]

Amazing content.thanx a lot for sharing

[@AdiTeman]

My pleasure

[@ShubhamKumar-is4ob]

plz add some lecture on tcl scripting and thanking you for the amazing video lecture you provide for the betterment of the students and freshers in vlsi industry. thanks alot

[@AdiTeman]

Hi Shubham, Actually, I may just record a lecture on TCL in the near future, if I can find time. Maybe your comment will motivate me to do it (...time, however, tends to be a problem these days :).

[@eda1058]

In 1:32:20 why do we draw data like that one going up the other down at the Same time but for clock There is onlu one line up and down in a row?

[@AdiTeman]

Hi, Thanks for the question. Some things we - experienced engineers - take for granted, since we're used to seeing them so often and we may not explain them (though I do vaguely remember explaining this in one of my lectures somewhere). The clock is very deterministic. Every clock period, it goes up once and down once and it does this repeatedly at a constant rate. Therefore, this is how we draw the clock signal. On the other hand, we don't know what the data is in a general case. It could be '1', could be '0', could stay constant and could toggle. Therefore, we draw it in that "changing" or "unknown" kind of way. It is supposed to represent "all cases" where we must take into account that any level can be there and where the X's are, it may be changing (it will be stable where the lines are straight).

[@ranveerdhawan5187]

Very nice explaination sir , its really precious .

[@AdiTeman]

Thank you!

[@sagarpatel2630]

Great lecture!

[@AdiTeman]

Thank you!

[@merrygo7189]

what is non sequential timing paths ?...why we are checking those paths in real design ....example ......reg > mux ...how can we can that non sequential path is valid or not ?

[@AdiTeman]

Hi Merrygo. Could you please explain your question a bit better? STA is used for sequential timing paths - in fact, the approach doesn't necessarily work for non-sequential paths. We do have in2reg, reg2out, and in2out paths that are not exactly inherently sequential (as they do not have a register as their start and/or end point), so we model the missing register(s) with input/output constraints. I am not sure what you mean by a path being "not valid". Thanks

[@epsilon4699]

Thanks Professor for the excellent video!! Question: Why do we perform min_transition checks on the design ? I understand the reason behind max_transition check, that is to avoid the crowbar current when the signal takes more time to change from one logic state to other. However if the signal transition is faster (min transition value) it is beneficial for us to meet timing with lesser delay. Isn't it ? Why do we make min_transition a design rule check ? Can you please clarify this standing question that I have been trying to get answer for a while now..

[@AdiTeman]

Hi Epsilon, that's a good question. The reasoning behind the min_transition is (primarily) the look up tables in the .lib file. Each standard cell is characterized according to a set of input transitions and output capacitances. These values are defined in the .lib file (and the characterization script, and usually there are 5 to 7 values for each. Adding more values means that more simulations have to be run during characterization and the .lib files become larger, and so, a basic range is chosen from some minimum (for both transition and capacitance) to some maximum with certain steps between (not necessarily uniform). If the characterization is done well, this range should cover the vast majority of the transitions and capacitances that will actually occur in a design. If, however, a particular transition or capacitance is either smaller than the minimum or larger than the maximum value, the interpolation done in the timing model loses validity, since the behavior is non-linear. Therefore, these values are considered "out of table" and are basically an error (since they provide inaccurate timing). To avoid being "out of table" minimum and maximum transitions and capacitances are defined. There could be other explanations, if you want, but they are secondary and non precise. For example, we don't want very fast transitions, because that means the previous stage is "too big" and you're wasting power and area. The rule of thumb is that both input and output transitions should be pretty much equivalent. Another explanation could be that too fast a transition could be a strong aggressor for coupled signals. But in all truth, the real reason is the .lib tables.

[@gino_raiola]

Kudos to you!

[@AdiTeman]

Thanks

[@carterlee287]

Thanks Sir for sharing your great knowledge. I have tiny question about your 4 category of timing path. Could you guide me a description of solution for each category's a timing violation(setup/hold)? I think, in R to R path case, it will be one of the solution for adding a F/F pipeline for setup violation and insert buffer for hold violation. But, No idea else at all. Could you guide for me for 3 else categories in setup and hold violation case?

[@AdiTeman]

So this is, in many ways, the holy grail of chip design, right? How do you get better timing... To the first order, you are correct. You can fix hold by adding a buffer on the data path to slow it down. To fix setup, you can add a sampling stage. However, neither of these are trivial. For hold, you have to find a point on your path that you can delay without affecting critical setup paths. Remember that many paths can go through a specific point, so just adding a delay may slow down the fast path, but it may also slow down the slow path. Luckily, the tools today are pretty good at finding where they can insert these delays to fix the violations (though, ECO placement and routing can result in insufficient and unexpected results). For setup, it's harder. You can't always just stick in a sampling stage wherever you want. You have to do this without changing the functionality. This often results in the insertion of many flip flops, which is costly in terms of area, power, and clock tree complexity. But there are many other optimization options. I discuss them in Lecture 4, starting at 1:11 (kzbin.info/www/bejne/ooXXY3-EbNOomJI). Things like upsizing gates, changing to LVT gates, restructuring the logic, cloning and restructuring the fanout tree, improving the placement and net routing... Sometimes, it requires going back to the design and changing the way the logic is written. Regarding the in2reg, reg2out and in2out paths, they are no different in essence than reg2reg. The difference is that you don't have the entire path in your scope, so you have to model the part that is outside your block. This is basically budgeting (how much delay can I allow inside my block). These budgets should be derived from the next level up the design hierarchy, but often, they are estimated or not thought about deeply enough, over-constraining the lower-level block. Easing these constraints will solve the problems, but you can only do this if you make sure that you actually can. Pay attention that after building a clock tree, the set_input/output_delay constraints get "messed up", since they introduce "fake" skew. I explain this briefly here and in the CTS lecture. Hope that helped.

[@thrilleracaste400]

Thank you very much sir! The video was very helpful and informative. Efforts appreciated!👍

[@AdiTeman]

Most welcome!

[@andrewvu1503]

Thank you for your videos. I am still a little confused about what the difference between a spec file and an sdc file is. I know spec is mainly used just for ccopt. What are the differences?

[@AdiTeman]

Hi Andrew. A "spec" in general is usually a text document, describing the system features/requirements, from which the entire design is derived. For Clock Tree Synthesis, in the past, there was a specific "CTS Spec" file in a proprietary format, but now (in CCOpt), you just give TCL commands that define settings, like all other Innovus tools. We often put this in a separate file to organize things. As for SDC, this is the timing constraints file. Again, you can input these commands in TCL, but to be compliant with other tools and vendors, it is usually good practice to write the timing constraints in SDC format and put them in a separate file that is read in during the flow. As for the difference between SDC and CCOpt constraints - this is a bit more deep and complicated. In general, SDC defines the static timing analysis and optimization constraints (or general physical implementation constraints), while CCOpt constrains are only for the clock tree synthesis. Usually they are related and so CCOpt can automatically generate the CCOpt constraints based on the SDC commands that are loaded into the design. However, once you have to deal with a non-trivial clock tree (which is usually the case), this automatic process doesn't hold up and you have to define things after a deep thought process. It is a type of art. Defining good CTS constraints takes a lot of experience and learning from past mistakes. In the end, the SDC constraints are with you throughout the flow, while the CCOpt constraints are only used during the CTS (CCOpt) stage. But it's a bit deeper than that.

[@krishnapatel6162]

Hi Professor, I had one query regarding providing IO constraints. On which criteria we decide on value of the delay while providing IO constraints using set_input_delay and set_output_delay. Thanks in advance!

[@AdiTeman]

Great question and one that is not easy to answer. In many cases it's just a rough guess (i.e., "half the clock cycle"), but that is not a methodology or a reasonable way to do it. The best way is in a top-down hierarchical approach, where we partition the design by defining several low level macros that will be implemented separately. In this case, the toplevel has the entire view of the timing and can "budget" delays to the lower levels. This flow can then write out an SDC with the required input and output delays, based on actual timing budget found at the toplevel. However, that assumes a top-down hierarchical flow, which is often not used for various reasons. When doing bottom-up (i.e., implementing the macro first, before integration at the top), you really have to "guesstimate" your IO delays based on knowledge of 1) how complex the path is inside your macro and 2) how complex the path is outside your macro. The idea is to make sure that when integrating at the toplevel (which comes relatively late in the project), we won't run into surprises due to badly defined IO delays. But this is hard and is often just plain done without much thought or effort. One more point is the off chip IO constraints at the top level. Here there are important constraints that come from the board/system level that must be taken care of inside the toplevel. This is often called "AC Timing" and outside the scope of this lecture series (unfortunately, there's a lot of company specific and protocol-specific "black magic" there). But it is quite important and needs to be taken into consideration.

[@mansishah2265]

Why recovery and removal check are not for assertion of reset? Why there is a problem of metastability for asynchronous input?

[@AdiTeman]

Hi Mansi. I will try to answer, if I understand your questions. Regarding Recovery and Removal checks - the problem is coming out of reset, not going into reset. Resetting a system is a harsh operation and it brings us to a predetermined, unique state. If you have a "timing violation" type thing on assertion of reset, it's not a problem, because the next clock cycle it will go into reset. No harm done. Coming out of reset, however, is the start of our sequential/operational mode and so it's important that everything is coherent and therefore recovery/removal checks need to be verified. Regarding asynchronous inputs - I'm not sure exactly what you mean, but asynchronous signals, in general - i.e., signals that are triggered by different non-synchronous clocks or some random source - cannot be tested for max/min-delay violations as we cannot define the relation between the launch and capture paths. This subject is covered in Lecture 8: Clock Tree Synthesis, starting at 1:12 minutes (kzbin.info/www/bejne/rqmaqqCuotalnbc)

[@MrSatyanshuu]

Thanks a lot for awesome series Prof. ! But I am not able to access the lecture slide, is there any issue with the lecture slide link given as the link above in the description? TIA.

[@AdiTeman]

Yes, I believe that the IT of Bar-Ilan University has put some access restrictions due to cybersecurity warnings. I will eventually move the lectures to an external server if they do not resolve this soon. Please feel free to contact me directly (e-mail) if you need a certain lecture PDF in the meantime.

[@AdiTeman]

My faculty website is back online www.eng.biu.ac.il/temanad/teaching/

[@jayparekh9768]

Best lecture!

[@AdiTeman]

Wow, thank you!

[@pedapudivasanth6305]

Sir i am new to learn VLSI PD COURSE all 10 lectures covers the syllabus or not....sir

[@AdiTeman]

Yes 100%

[@quanhong6503]

hi Adi Teman, thanks a lot for uploading such a precious series on a subject which is rarely taught online like this (digital VLSI design), can i ask you when the next English video (lecture 6) of this series will be uploaded ? I'm a student with a VLSI engineering background so i'm looking forward to seeing your English videos soon ...

[@AdiTeman]

Hi Quan, Thanks for the kind words! Lecture 6 will take probably more than a week from now, but it will be here before you know it!

[@phuongtuannguyen9415]

Hi Anh Quân, e là Tuấn, e mới tìm hiểu về digital VlSI, A có thể cho e xin contact để trao đổi ko ạ?

[@nantes9807]

Sir, Usually, tcq is greater or smaller that tsetup & thold ?

[@AdiTeman]

Hi, Actually, in many ways tcq is independent of tsetup and thold and so there is no answer to your question. In Lecture 7 of my VLSI course, I explain how to construct a general flip flop standard cell and how to calculate these parameters for it, which could remove some of the mystery around this. See this lecture: kzbin.info/www/bejne/j37UY2iYjJKNa8k In any case, each of these parameters is heavily dependent on the circuit design of the underlying block and the values can vary a lot. For the flip flop I show in that lecture, tcq is very short and thold is negative, while tsetup is quite substantial. For other implementations or other circuits (e.g., SRAMs) these relations can be totally different. In addition, process variations (corners) can change the relations between these parameters.

[@bibekanandabora]

Thanks alot....very helpful. Thanks

[@harihara.t]

Enjoyed a lot! Thanks

[@AdiTeman]

Glad you enjoyed it!

[@nazianazneen8446]

Thank you so much for uploading this STA video...it's very helpful...and I am eagerly waiting for your upcoming physical design specially CTS video...you explained it in very nice way

[@AdiTeman]

You're welcome! The next video will be on Floorplanning, followed by Placement. Only after that will I be recording the CTS video, so it will take close to a month, but I hope it will be worth the wait. Enjoy!

[@nazianazneen8446]

@@AdiTeman ya sure sir I will wait... thank you for your amazing video and instant reply

[@nazianazneen8446]

@@AdiTeman ya sure sir I will wait... thank you for your amazing video and instant reply

[@RahulTiwari-ec2df]

Thanks sir for awesome lectures..Are this regular classroom lectures of your university?

[@AdiTeman]

Yes, these courses are given in the Faculty of Engineering at Bar-Ilan University (engineering.biu.ac.il/en). You can also find information about the EnICS Labs Impact Center at our website enicslabs.com/

[@VLSITechnology]

Many thanks

[@AdiTeman]

You are welcome

[@debarunsaha8485]

Sir can u explain/elaborate min delay concept once more? How it passes through several registers during the same clock cycle?

[@AdiTeman]

Yes. I can try. Assume you have positive clock skew, i.e., the clock edge rises at the launch register and then is delayed before rising at the capture register. During that time, the launched data (triggered by the clock edge that has already arrived at the launch register) starts to propagate through the data path. If the data arrives at its endpoint (the capture register) before the clock edge then once the edge arrives, it will capture the new data, rather than the data that was there when the launch clock edge rose. Therefore, the launch data basically skipped through this register and is propagated all the way to the next endpoint.

[@debarunsaha8485]

@@AdiTeman okay sir.

[@debarunsaha8485]

Sir,Can you explain the hold timing on half-cycle path,Is it really depends on the frequency/time period?

[@AdiTeman]

Hi Devarun, Actually, this is a confusing subject, but the answer is simple if you can get your head around it. The definitions that were given are true for all max-delay/min-delay timing paths. The question is what constitutes the launch and capture paths. If, for example, a launch path is triggered by a rising edge but the endpoint is a falling edge triggered flip flop, you would get a half-cycle path. To understand the timing (both hold and setup) you just have to follow the paths. Let's define that the launch path was triggered at time 0 and took tlaunch to propagate to the endpoint. The capture path, on the other hand, was launched on the opposite phase of the clock (as the endpoint is negative edge sensitive). So for hold, when you want a worse case on the capture path relative to the launch path, we will take the triggered edge delayed by half a cycle (assuming a 50% duty cycle on the clock). In other words, the capture path starts at T/2 instead of at 0. It then propagates to the endpoint (we'll call this tcapture) and so our timing constraint, which is always Tlaunch>Tcapture for hold, can be written as: 0+tlaunch>T/2+tcapture+thold

[@debarunsaha8485]

Sir as I learnt,the equation is T/2+Tcq+Tcombo>Thold+Tskew+Thu.

[@durgaprasad5369]

sir it's great thanks a lot.

[@SandeepKumar-st3lo]

Firstly thanks for the great lecture. I see that it should be report_timing -format (not -field). at 1:40 hrs

[@AdiTeman]

You are correct, but this is not exactly a "mistake". EDA companies often do things that are out of our control. When I made the video, the current version of Innovus used the option "-field". Following your comment, I checked and in the latest version of documentation (20.12) they have changed it "back" to "-format" (which is what it was in the legacy UI command). Thanks for the comment! I will see if I can edit this out at some point.

[@balajisrinivas5330]

Thank you!!

[@AdiTeman]

You're more than welcome!

[@RedMoon543]

Wonderful lecture

[@AdiTeman]

Many thanks

[@ankitsingh8813]

thanks sir for this

[@AdiTeman]

Most welcome

[@sksson1]

Awesome.... Perfect....:) Thanks

[@AdiTeman]

You're welcome!

[@aradhanakumari4029]

Sir thank u so much .this video is very important for us who is working in industry . Sir can send me the PPT of STA please?

[@AdiTeman]

Hi Aradhana. All the slide notes are posted on my website in the video description. Thanks.

[@kevinthomas1618]

explanation is kinda confusing

[@AdiTeman]

Sorry for that. If you could elaborate, I could try to improve it.

[@neelakantm547]

Hvv

[@AdiTeman]

Hi Neelakant. I am not familiar with this acronym. I hope it's something positive :)