DVD Lecture 7: Standard Cell Placement

[@gb92603]

I am a VLSI PhD student and I use all of your notes continuously to refer too. You are doing a great service for all of us, thanks!

[@AdiTeman]

You're very welcome!

[@abhishekchaubey7280]

Thanks sir your videos are very helpful to understand the concepts and different terminologies.

[@AdiTeman]

Glad to hear that! Your kind words give me motivation to make more of them!

[@anuragec1026]

your lectures are addictive 😊

[@AdiTeman]

Glad to hear that

[@amanbarsaiyan7678]

I think in analytical placement cost function there is square root is their in formula of quadratic wire length between two points then its become root of 13 that is less than 5 unit as we find in HPWL.

[@AdiTeman]

Hi Aman, If I understand your comment correctly, the square root is proportional to the non-square root calculation and so it doesn't really matter for the calculation. It will affect the weight of the distance, but this is anyway calibrated with the division factor of the clique model. Note that HPWL and Quadratic Wirelength are two different wirelength estimators and should not be compared in terms of value. Indeed, both should express a relative wirelength (i.e., this net is longer than that one), but you cannot compare "apples and oranges" and so don't try to...

[@amanbarsaiyan7678]

@@AdiTeman ok sir

[@mohankrishnapeddi4109]

hi sir can u tell me where did you explained about the physical cells

[@AdiTeman]

Hi, in Lecture 3, when I talk about standard cell libraries. I also may discuss them a bit in the last lecture in the course, about signoff.

[@lalithsamanthapuri2055]

@Adi Teman sir,how AI affects the VLSI chip designing..??What is the relation?? what should we(VLSI Physical Design Engineers) should update ourselves about the latest technologies or languages in future...!!

[@AdiTeman]

Hi Lalith. I am not sure I understand your question, but to try and provide a response - AI is a bit independent and a bit connected. On the implementation side, new tools can use AI approaches to reach better solutions for EDA problems. On the usage side, AI can benefit from efficient architectures that are targeted at this type of computation.

[@lalithsamanthapuri2055]

@@AdiTeman Is there any problem for VLSI Physical Design Engineers in coming years as we are gonna hit a saturation region...!

[@lalithsamanthapuri2055]

@@mewantedbyme1 As a 22 year old recent graduate I have a solid knowledge over coding and Mathematical analysis.So,It's easy to switch for me and I did that.. I switched to AI recently which is related to Chip designing. "Don't worry about myself,just take care about yourself properly man...!"

[@AdiTeman]

Hi Lalith, I'm really sorry that I never responded - I didn't see your comment. But now I can say that I have a better answer. If you've been following the news over the last months, you see that there is a huge chip shortage. Maybe that doesn't specifically relate to chip designers (more to fabs), but it's part of the overall trend that everyone needs more and more chips. In Israel, for example, all the big guys are either opening huge R&D centers or expanding (in the last months, huge announcements by Google, Microsoft, Facebook, Intel, Amazon). They all need chip designers! So you made the right move!

[@Editzzor109]

can we do cell padding for pin density

[@AdiTeman]

Hi, Yes, indeed you can pad cells and that will reduce the pin density. Of course, this comes at the cost of extra area, but it could be useful to apply to certain hierarchies. I guess this is the same as applying a lower target utilization, though going at it from "a different direction". As a side note, cell padding is usually used for things like leaving space to put decaps next to flip flops and clock buffers to improve the dI/dt drop near the toggling clocks. But it could be used as you suggested, as well.

[@rahulbhat3409]

Thank you for the lectures, these are awesome!. I had a couple of questions: 1. Since the macros are fixed before the standard cell placement, will the tool be aware of this and avoid standard cell overlapping macros? If yes then would this affect the recursive partitioning in any way. 2. Is the trail route step to check if we meet timing requirements or to check routability of design or both? Thanks in advance

[@AdiTeman]

1) Yes. I think this is something I am trying to emphasize in the limitations of the clustering and the algorithm in general. The actual tools need to take care of this and many other restrictions. How they do it is another question, since this can lead to much loss of optimality. But they could place them without looking at the macros and then legalize to remove overlaps, or they could do something like create the partitions while taking into account the macro utilization inside the partition. But these details are beyond the scope of this lecture, though I'm sure there is some literature about how to do this effectively and efficiently. 2) So I would say both. It probably depends on the optimization targets selected in the tool (e.g., "congestion aware" and/or "timing aware"). The tools do not elaborate on this very much, but the trial route is for sure a necessary tool to apply such incremental optimizations.

[@varunbajpai8664]

@Adi Teman can you tell me why we fix hard macros at floorplan stage and it is necessary to fix it? Why we can't fix it at placement stage ??

[@AdiTeman]

So I don't exactly have a straightforward or 100% accurate answer, but I'll try. One thing is that the placement algorithms deal with standard cells, where each cell is very small and can be treated as a sizeless point. Macros, on the other hand, are big and so this type of assumption will result in really bad decisions, probably. Another point is that Macros are big and important and "drive" the overall placement in the design, in a similar fashion that pins are "anchors" that constrain where each module will be placed. So, since there are relatively few (...relatively) of these and they have a strong effect on the results, we apply more control by placing them manually and fixing them. To that end, they also affect the power distribution and blockage of routing channels and other things that all basically have an effect on the final physical design. A final point is that there are many algorithms and tools for automatic floorplanning and you can find them inside the commercial tools. However, as happens with many automatic tools that are available for various applications, they have (so far, as far as I know) not caught on in industry. I would suggest to give them a try and see how they work for you, as they can/could indeed save a lot of time and possibly reach a better solution than you can arrive at manually.

[@abhishekchaubey7280]

Sir what is heuristic?

[@AdiTeman]

Hi Abhishek. From the definition on Wikipedia, a heuristic is any approach to problem solving or self-discovery that employs a practical method that is not guaranteed to be optimal, perfect, or rational, but is nevertheless sufficient for reaching an immediate, short-term goal or approximation. In other words, it is an algorithm that is NOT OPTIMAL, but it's a "good guess". We use heuristics on any optimization problems that are too hard to solve in a finite amount of time (N-P complete problems). Instead, we apply an approach that we know is better than just some random search, so we can probably find a pretty good solution, though it will not be optimal. Just as a side note, if we have an optimal solution for a problem, then usually that is a "done deal", so we don't really need to research the problem anymore. However, very few real life complex problems have such a (known) optimal solution, at least if you take into consideration all of the assumptions that have to be made, which may be sub-optimal.

[@nazianazneen8446]

Nice video 🙏sir I have a job interview on 3rd Jan ...if possibly please upload the CTS part asap