DVD - Lecture 9: Routing

Bar-Ilan University 83-612: Digital VLSI Design
This is Lecture 9 of the Digital VLSI Design course at Bar-Ilan University. In this course, I cover the basics of Chip Implementation, from designing the logic (RTL) to providing a layout ready for fabrication (GDS).
Lecture 9 covers the routing process, including basic approaches to maze routing algorithms and how routing is carried out in practice within EDA tools.
Lecture slides can be found on the EnICS Labs web site at:
enicslabs.com/...
All rights reserved:
Prof. Adam Teman
Emerging nanoscaled Integrated Circuits and Systems (EnICS) Labs
Faculty of Engineering, Bar-Ilan University

[@NasirKhanPAK]

Sir you are great. I learnt a lot from your lectures. Thanks thanks a lot.........

[@AdiTeman]

My pleasure!

[@rohanyadala9096]

Nicely explained 👌

[@AdiTeman]

Thank you 🙂

[@nazianazneen8446]

Very nice explanation sir.. thank you so much

[@AdiTeman]

You're welcome!

[@merrygo7189]

Very good explanation sir..

[@AdiTeman]

Thank you!

[@rahulbhat3409]

Had a few doubts 1. If we define routing directions for a particular layer, how would there be possibility for jog, in other words wouldn't we only have horizontal or vertical tracks in a given layer? 2. Would the via dimensions also change for different metal layers or do we use more vias for thicker metal layers?

[@AdiTeman]

Hi Rahul, 1) Routing tracks are (at least in older processes) more of a directive rather than a hard constraint. In other words, you can route in the wrong direction, but you should only do this if it's a little tiny jog or there is no other viable solution. In harder constrained technologies (e.g., quadruple patterned), this may no longer be true, but I wasn't referring to those. 2) Yes, the via dimension drastically change for different metal thicknesses, as well as the DRC rules for these vias. So a VIA7 will be much much much larger than a VIA1.

[@rahulbhat3409]

thank you for the clarification adi !