DVD Lecture 11: Sign Off and Chip Finishing - Part 2

[@amarsamudrala1060]

Hi sir what is difference between hierarchical and flat synthesis

[@AdiTeman]

In general, in VLSI CAD (and many other engineering processes), "hierarchical" means that we "divide and conquer". In other words, we will break the design into several parts (sometimes break the parts into additional parts...) and run the process on them independently. Then we will take the results and integrate them into a higher level process. So for synthesis, let's take an example of an SoC with 4 CPU cores. We could run "flat" synthesis, which means we give the tool all the RTL and have it deal with 4X the number of gates in one CPU core, plus the rest of the SoC logic. Or we could do it hierarchically, i.e., synthesize the core independently and then run a toplevel synthesis on the SoC, where we instantiate the synthesized netlist of the core 4 times, thereby reducing the complexity of the synthesis.

[@thaodgn]

Hi Professor, your video lecture is great.BTW, the hyperlink of lecture slides is no lonnger access. Could you update a new link? Thank you sir :)

[@AdiTeman]

Yes, I believe that the IT of Bar-Ilan University has put some access restrictions due to cybersecurity warnings. I will eventually move the lectures to an external server if they do not resolve this soon. Please feel free to contact me directly (e-mail) if you need a certain lecture PDF in the meantime.

[@KousalyaIndravath-IK]

Thank you so much sir.

[@AdiTeman]

Most welcome

[@mynameisnotamd2923]

Is the next video in the playlist (about investment from Cooper Academy) related to VLSI Design?

[@AdiTeman]

No, this is a mistake (GUI "feature" of KZbin... Happens to me once in a while). Thanks for pointing this out. I will fix it :)

[@mynameisnotamd2923]

@@AdiTeman Thanks a lot for your time and effort. This video series is the most comprehensive video series available freely that I could find covering the RTL2GDS flow. Greatly helped me during my preparation for interviews.