Electromigration in VLSI Design | What is electromigration | How to prevent Electromigration

[@theebanraj5229]

Very good explanation. Thank you sir

[@TeamVLSI]

So nice of you. For more such videos, stay tune the channel.

[@ajiths1689]

very nice video and lecture

[@sujendramanik5068]

Very Help full, Thank you.

[@TeamVLSI]

You're welcome Sujendra!

[@asmisharma3163]

Thank you so much for these videos. Extremely helpful. Also, please share the Physical verification concepts (perhaps a series, like the one with the file formats you have shared). Thank you so much.

[@TeamVLSI]

Thanks a lot Asmi. Said series is already in my bucket, will be shared soon.

[@abishekguggari1180]

excellent information.really helpful.keep it up.thank u

[@TeamVLSI]

Thanks abishek!

[@yennarascalamindit2632]

Thank you for this video. Was really helpful.

[@TeamVLSI]

Welcome Yenna! Glad it was helpful! Stay connected and keep learning...

[@Jamboreeni]

Can you please explain how reducing wire length will help in EM?

[@Jamboreeni]

Sorry got it, Blech length

[@NomadMaveric]

Thanks Sir. The tutorials are very helpful.

[@TeamVLSI]

Thanks @Praphulla !

[@mattoomueen]

Thank you. It's really helpful. Cheers!

[@TeamVLSI]

Welcome Mueen! It's our pleasure. :)

[@ArunKumar-wu4px]

Awesome Explanation ...what about the EM tool used in ICC and Mentor Graphics..in which stage we will check electromigration...

[@LAFAMA5759]

Great Job!

[@TeamVLSI]

Thanks @Fernando !

[@vinodk8125]

Thank you..its really helpful. Can you explain the difference between EM, ESD & Antenna effect ?? Which stage we can see these effects while doing the manufacturing ??

[@TeamVLSI]

Thanks Vinod. I have noted your request, will try to cover in future.

[@darpankumar9499]

Thank you sir for these videos ... I have one question related to EM, in which nets EM take place...

[@maltikumari8677]

Thanks for uploading..

[@TeamVLSI]

Welcome @Malti Keep encouraging us!!

[@vinodkumarck1919]

Good work 👏👏

[@TeamVLSI]

Thank you so much @Vinod 😀

[@vinodkumarck1919]

@@TeamVLSI Hi, can you explain how reducing frequency will reduce EM.

[@asyameliksetyan1283]

Thank you too.

[@TeamVLSI]

Welcome Asya, Keep learning!

[@trivenik9219]

What is the command to check EM IR in icc2 can you please help me

[@AngelPl4y3r]

This video is amazing and you do a great job at explaining the problem and how the industry have dealt with it, specially on how its a process dependent problem to a great extent but how the design side of things can contribute to mitigate the problem. THANKS!

[@TeamVLSI]

You are welcome.

[@akhilalla3247]

you mentioned out of 5 chips 1 chip is getting failed due to EM? for suppose, i have one plus phone with Snapdragon chip like wise i have 5 mobiles, In this as you told, remaining four are working properly why only one is having this issue(I mean all has to face this issue why only is facing this issue) and also you told this issue will come even after years, how does current increases in the chip after using for years? i mean suppose till 5 years i have used the mobile there is no problem upto 5 years. but suddenly how current in the metal gets increased? i fabricated as per design rules and it worked for 5 years only. how come the current in the chip is within the limit for 5 years? how current suddenly increasing in the design? please clear my doubt sir Thank you for all your videos. it's really helpful to gain more knowledge on this concepts. I started reading your blogs also. great knowledge sir.

[@TeamVLSI]

Thanks Akhil to writing your doubts is such a clear way. You could also use timestamp of video to indicate the point on which respect you have doubt. I did not got the first part of question. In second part explanation is like that. "A chip may face EM issue after some times" is valid and it is not related to increase of current. the movement of atom is due to moment transfer might be very slow and its effect will come after some years. Although there is reliability test of chip for this, in which we can predict the characteristics of chip after few years. Another thing is there is aging effect in transistors which affect the performance of a chip, that is related to current of transistors. So fact is that the current of transistors at the time of fabrication is not going to be same after 10 years later. Thanks.

[@akhilalla3247]

@@TeamVLSI Thank you for the info sir

[@sharathseshadri3634]

Keep length short ???

[@csst29]

what is F wind?

[@gokulapriya4984]

Please do share remaining issue...of the following...in this video

[@TeamVLSI]

Sure Gokula, It will be published soon.

[@gokulapriya4984]

And also share a scripts file.... Like floorplan.tcl,pace.tcl,route.tcl,mmmc,tcl....

[@TeamVLSI]

You can check now, this series has completed now.

[@gokulapriya4984]

Thank you so much!!

[@komatinenibharathkumar8291]

thank you so much for yur information. Can u please upload more problems regarding EM?

[@jyothico8812]

Very nice and detailed teaching. Could you please clear my doubt how is reducing buffer size in clock lines taking care of EM? Thank you

[@TeamVLSI]

Higher the drive strength of buffer, will require more current... more susceptible to EM.

[@huhuu-mq1tx]

@@TeamVLSI im confused, i thought if the area is bigger, current density will be lower, thus can avoid EM. pls explain... if we upsize a cell, wouldn't it help EM?

[@wilsonhung4369]

@@huhuu-mq1tx I think what matters is the wire, where EM takes place, but not the buffer. So larger buffer causes more current for the wires connected to it and thus more EM risks.

[@mapytekh]

Nice one!...

[@TeamVLSI]

Thank You :)