Latch-up prevention in CMOS | Various techniques for latch-up prevention | Issues in Physical design

[@rajgandhi4042]

At 19:30, you told that there are 4 collector around standard cell and minority charge can be collected to avoid latch up, but I didn't understand how did the tap cells present above and below standard cell can collect minority charge carrier because tap cell's p substrate and n well is not overlapping with p substrate and n well of the standard cell. Thanks

[@TeamVLSI]

Hi Raj, Thanks for your feedback. I will provide a better elaboration soon.

[@venkatnarayana2068]

could you please tell guard band importance in sense amplifier

[@AnilKumar-hl7oq]

informative and satisfied !! osm

[@TeamVLSI]

Thanks Anil :)

[@anhtuan2086]

English is not the negative language of me, If you can putting sub for video, it helps me very much is clear. thank you!

[@TeamVLSI]

Thank you! We will try.

[@sth4someone912]

Could you please prepare some videos on ESD/IO rings and how to place them in ICC? Thanks

[@TeamVLSI]

Yes sure, But some time later.

[@sb6701]

Good information, thank you. But I have a query can u please explain. Latchup is forming bcz of tap resistance also and in below 65nm the std cell layout is without tap cells... then below 65nm how latchup formed and in above 65nm how tapcells prevents latchup.. sorry if I’m asking anything wrong.

[@TeamVLSI]

Thanks, Bindu Latch-up is triggered because of the high well and Substrate resistance (low doped regions) [Not because of tap cells]. This resistance caused a sufficient voltage drop to make emitter-base junction forward bias. Because of tap cells in lower technology, the flow of minority carriers gets dispersed, which reduce the voltage drop across base-emitter junction and further prevent turning on the BJT. In larger technology, generally we use guard rings.

[@sb6701]

Thanks for your reply. :)

[@mohammedafzal534]

Good explanation! But i have a question you shown guarding in cross sectional view by placing n+ or p+ by the sides of dissuions,can't we have n+ or p+ at the bottom along with sides? May interviewer will accept it or not if we shown like that?

[@TeamVLSI]

Could you please ask your question in more clear way. Sorry I have not got the question clearly.

[@mohammedafzal534]

How will you represent the guarding in cross sectional view?

[@TeamVLSI]

Hi Afzal, Pause the video at 6:12 and see the image of bottom left side, that is the cross sectional representation of guard ring.

[@mohammedafzal534]

Ya sir i watched that one, that's why i got a doubt. In layout we surround the device with guarding but in cross sectional view you shown the guarding in between pmos & nmos only right.Is it correct to show the guarding like that, i don't know to confirm it i am asking. Please clarify it sir

[@TeamVLSI]

Hi Afzal Actually, there are various ways to put the guard rings, I have shown there only a way how can we prevent Latch-up using guard ring in an inverter circuit. In fact you can put the guard ring all around your circuit, between the circuit and there are many more techniques.

[@saijagadeesh1708]

Sorry sir , I didn't get much clarity about how exactly these well tap cell will prevent latch up issue?

[@TeamVLSI]

Hi Sai, Thanks, Let me try to make it clear. Try to understand this in the simplest way as: 1. To prevent the latchup we need to connect the nwell to VDD and pwell to VSS. 2. Tap cells are doing this job only.

[@shyamnair8912]

Hi Sir,, How is the TAP2TAP distance calculated? I see in different technology the TAP2TAP distance is different.. How is this calculation made?

[@TeamVLSI]

Hi Shyam, Yes it is technology node dependent parameters. Generally while developing a new node, these are characterized and passed to designer.

[@ashmeetjheeta4323]

Hi I have a query what is the difference between contact and via ?

[@TeamVLSI]

Hi Ashmeet, Really a good question! Basically the contacts is a material used to connect the diffusion and the lowest metal layer or Poly to lowest metal. Whereas the via is used to connect the metals. like M1 to M2 , Via1 is used. M2 to M3, Via2 is used.

[@tanimadas2014]

@@TeamVLSI Why we can't use guard ring in standard cell?

[@ayushdhamani1238]

How welltap is actually preventing latchup ? That is not yet clear .

[@TeamVLSI]

Hi Ayush, Thanks, Let me try to make it clear. Try to understand this in the simplest way as: 1. To prevent the latchup we need to connect the nwell to VDD and pwell to VSS. 2. Tap cells are doing this job only.

[@ayushdhamani1238]

Thanks.. I understood that..but how tapping is preventing latchup..what was explained is that tapcell helps to reduce area , but in regular stdcell in which nwell and psubstrate are tapped with vdd and gnd..does latchup occur in those cells ?

[@prasannashanbhogue4070]

Sir, but you haven't explained how tap cells prevent Latch-up problem. :(

[@TeamVLSI]

Hi Prasanna, Thanks for your concerns. I have just revisited the video and I found I have talked about it at 19:25 . But If you still need more clarity. I can make it more simple. I will try to publish a video focused on that.