Antenna Effect Prevention Techniques in VLSI Design

[@vinodkumarck1919]

Thanks for the video and this initiative

[@TeamVLSI]

Welcome @Vinod, Its our pleasure. Keep connected and supporting us.

[@ArunKumar-wu4px]

Clear explanation....about antenna prevention technique...kindly share command to insert metal hoping, diode insertion using innovous or ICC tool

[@TeamVLSI]

Let me check.

[@analoglayout]

Congratulations , for this initiative

[@TeamVLSI]

Thank you so much.

[@akashwayal8797]

Is CMP removes the chrges on the interconnect?

[@TeamVLSI]

Yes.

[@mp-qk9eq]

Thank you very much for this informative video. By any chance, do you have videos regarding layout parasitic extraction?

[@TeamVLSI]

you can check a video in following playlist on LVS and PEX kzbin.info/aero/PLC7JCwKQnjL5fR-0F8DPZYUbZVG81PC5E

[@Narennmallya]

sir so by default in twin tub process for a cmos circuit, there wont be latchup and antenna effect right, since in that case also there is an extra implant layer that forms a reverse biased diode( similar analogy to antenna diode insertion to prevent antenna effect)?

[@nanoelectronicsdemystified]

Shouldn't the diode be in forward bias? in reverse bias, how will it create path to ground? Because the intention is to bypass the static charges through the least resistive path, which we are gonna get in forward bias and not in reverse bias. Correct me if I am wrong.

[@TeamVLSI]

No Kishan, Antenna diode is always in reverse biased. It should not conduct in normal operation. It should only conduct at high temp during plasma etching while fabrication process.

[@ArunKumar-wu4px]

Do you have videos for DRC, LVS, LEC using innovous or ICC tool...it will be very helpful...

[@TeamVLSI]

Not in ICC, But have videos based on Cadence and Mentor tool in custom layout design series.

[@kiran7640]

Nice video sir .Do more videos

[@TeamVLSI]

Thanks Kiran :)

[@nirmalnikitha8596]

why is the diode inserted in reverse bias sir

[@TeamVLSI]

Hi Nirmal, Because a reverse-biased diode will not conduct in normal conditions. But it will conduct during the fabrication process as that time temperature is very high and so the diode will be reverse saturation state.

[@rohanyadala9096]

Excellent

[@karthickramki4062]

What is command to add reverse diode in innouvs ??

[@sridharnarayana3557]

Thanks for Video, Let's assume I don't have a room to go for higer metal ,and I don't have any area to add Dummy transistor or diode,in this case How we can Slove antenna violation? 2. assume getting antenna in Metal 3 ,and I don't have room to go for higher metals,no area left. Can we use lower metal to get rid of Antenna violation? Thanks

[@TeamVLSI]

Welcome @Sridhar, Good question. Yes, We can do.

[@sridharnarayana3557]

@@TeamVLSI But How lower metal will reduce antenna violation? Can you please explain in detail Thanks for taking time from your busy schedule.

[@pavangudipati6]

Thank u sir

[@TeamVLSI]

you are welcome @Pa1

[@user-ep4hz6nq5y]

Pn junction diode when operated at reverse brkdown voltage get damaged .Then how we can use it?

[@TeamVLSI]

Actually at high temperature the the reverse connected antenna diode, will go on reverse saturation region. And in case this diode gets breakdown, then also it is not going to affect the functionality of circuit as we wanted not to conduct this diode anytime rather the plasma etching to discharge the excess charges.

[@StayInBliss]

thankyou sir

[@TeamVLSI]

You are welcome :)

[@Anjay17680]

why we use diode in reverse bias?

[@TeamVLSI]

Hi 16:18 See the explanation from this point. Because a reverse bias connected diode has no effect on the normal operation but while plasma etching at high temperature this diode will be thermally unstable and is in reverse saturation region which will help to discharge the extra charges on the gate. And if it is in forward bias, signal on the gate terminal will be grounded.

[@harishbv7092]

Thank u sir

[@TeamVLSI]

Welcome Harish :)