Electronics Interview Questions: STA part 1

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ElectroTuts

ElectroTuts

Күн бұрын

Пікірлер: 39
@Deepakkumar-tq1xv
@Deepakkumar-tq1xv 5 жыл бұрын
Best ever explanation for STA. Keep posting such videos..
@electroTuts
@electroTuts 5 жыл бұрын
Thanks for the support !!
@hm6936
@hm6936 4 жыл бұрын
When adding Buffer time (skew) to setup time equation (time 7:00) i think it should be tcq+tpd+tsetup+tb
@ANKITMAURYA-sj9dg
@ANKITMAURYA-sj9dg 4 жыл бұрын
same doubt regarding this
@mayureshjoshi7494
@mayureshjoshi7494 4 жыл бұрын
@@ANKITMAURYA-sj9dg T is the total time period of the clock path. If we are inserting a buffer of delay tb in the clock path, the total time of the clock path will be T+tb
@jiaabhiraaj9449
@jiaabhiraaj9449 4 жыл бұрын
Bahot badhiya content
@cburrito1000
@cburrito1000 4 жыл бұрын
nice list of videos. very useful and understandable
@anirudhkashyap5393
@anirudhkashyap5393 4 жыл бұрын
Could you explain the hold time constraints for the inverted clock case because I am getting it as tcq + tpd >= thold + tinv + T/2
@rambalaji725
@rambalaji725 4 жыл бұрын
Me too
@rambalaji725
@rambalaji725 4 жыл бұрын
Is it wrong in the video?
@aashnajain6519
@aashnajain6519 3 жыл бұрын
Me too
@rohitgaykhe9883
@rohitgaykhe9883 3 жыл бұрын
me too
@tuongluongthanh2030
@tuongluongthanh2030 5 жыл бұрын
thank you for your presentation !
@GaneshPatil-vj1qp
@GaneshPatil-vj1qp 4 жыл бұрын
Too good explanation on this topic so far i have seen anywhere👌👏best👍Thank you😊
@HardwareNinja
@HardwareNinja 3 жыл бұрын
Hi Ganesh, check us out for engineering interview related questions. We'd love to hear your feedback! kzbin.info/door/7h3PROcX7Zgx00alQokJ-w
@shashikantsingh4993
@shashikantsingh4993 5 жыл бұрын
good work bro...it is really helpful
@pavankumarreddy7888
@pavankumarreddy7888 5 жыл бұрын
I dont think there will be any hold time violation for the clock diagram for the case of inverted clock given to the 2nd FF becz.. Anyways data will be held constant by the 1st FF while 2nd FF is sampling the data if the Set- up time constraint is met.
@kalyan157
@kalyan157 6 жыл бұрын
Heyy you are excellent.Thanks a lot.Please do more
@electroTuts
@electroTuts 6 жыл бұрын
Thanks for your support Kalyan, will make more videos as soon as possible!
@gudipatiramu5984
@gudipatiramu5984 6 жыл бұрын
I really liked the Inverter Question. But, detail explanation would be much more helpful.
@harshavardhanmittapalli5605
@harshavardhanmittapalli5605 6 жыл бұрын
Hi, why in the inverted clock case setup time check is with respect to same clock edge (after all it can be seen as a delayed clock with clock skew equal to inverter delay plus T/2).why not with respect to next clock edge??
@electroTuts
@electroTuts 6 жыл бұрын
great question!! You can do in that way also, then you have to meet the setup constraint of the next clock edge and hold constraint of the same clock edge. Then, STC becomes tcq + tpd + tsetup = tinv + T/2 + thold Depending on the delays between the 2 flip flops, the case shown in the video or the case you have considered should be choosen. I hope that I answered your question!!
@harshavardhanmittapalli5605
@harshavardhanmittapalli5605 6 жыл бұрын
Thanks for the reply @electroTuts. So it all depends upon the delay. But if we consider the case that was illustrated in the video then the output is available before the second clock cycle ( i mean before second edge occurs). We expect the output to be available after 2 clock cycles as we have 2 FF's. As it was the case in clock with out inverter.
@electroTuts
@electroTuts 6 жыл бұрын
Exactly !!
@harshavardhanmittapalli5605
@harshavardhanmittapalli5605 6 жыл бұрын
So in that case the data that was available at the input of second FF is overwritten.
@manojharshavardhan2385
@manojharshavardhan2385 3 жыл бұрын
So basically in this case we consider the hold analysis for current clock edge and the setup analysis for the next clock edge.
@MichaelAaronBerger
@MichaelAaronBerger 3 жыл бұрын
As everybody has stated, it should be tcq + tpd >= thold + tinv + T/2. since in his example, at -t/2 on rising edge is before the first flipflop even started.
@HardwareNinja
@HardwareNinja 3 жыл бұрын
Hi Michael, check us out for engineering interview related questions. We'd love to hear your feedback! kzbin.info/door/7h3PROcX7Zgx00alQokJ-w
@priyasahoo4280
@priyasahoo4280 4 жыл бұрын
as I have studied hold violation doesn't depend on clock period but here in case of inverter we see it is depending on T. please clarify.
@akshaygehi11
@akshaygehi11 4 жыл бұрын
I have the same question.
@HardwareNinja
@HardwareNinja 3 жыл бұрын
Hi Priya, check us out for engineering interview related questions. We'd love to hear your feedback! kzbin.info/door/7h3PROcX7Zgx00alQokJ-w
@007DARP
@007DARP 6 жыл бұрын
I watched all your videos regarding Timing Analysis. In the second Video you did the analysis considering clock skew and in the third with buffer. Shouldn't the Static time analysis equation of both will be the same? Just like the Hold time Analysis. Because Clock Skew and Buffer both are adding the delay in the clock of the second Flipflop.
@vlsikr
@vlsikr 3 жыл бұрын
Nice. Setup-time Violation or Hold-Time Violation, which one is worse?
@HardwareNinja
@HardwareNinja 3 жыл бұрын
Hi, check us out for engineering interview related questions. We'd love to hear your feedback! kzbin.info/door/7h3PROcX7Zgx00alQokJ-w
@rohitgaykhe9883
@rohitgaykhe9883 3 жыл бұрын
explain once again the last HTC when inverter is added.
@RandomHubbb
@RandomHubbb 4 жыл бұрын
the content is great, thank you. but i have an unrelated question : I like your handwriting and the pen you are using. What brand and type of pen is that? i keep looking at the stores and could not find a similar tipped pen so far :)
@bitopantalukdar9820
@bitopantalukdar9820 5 жыл бұрын
The way you are holding the seems as if your index finger will break sir.....
@maheshmahi2328
@maheshmahi2328 4 жыл бұрын
Music is annoying and very weird
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