Best ever explanation for STA. Keep posting such videos..
@electroTuts5 жыл бұрын
Thanks for the support !!
@hm69364 жыл бұрын
When adding Buffer time (skew) to setup time equation (time 7:00) i think it should be tcq+tpd+tsetup+tb
@ANKITMAURYA-sj9dg4 жыл бұрын
same doubt regarding this
@mayureshjoshi74944 жыл бұрын
@@ANKITMAURYA-sj9dg T is the total time period of the clock path. If we are inserting a buffer of delay tb in the clock path, the total time of the clock path will be T+tb
@jiaabhiraaj94494 жыл бұрын
Bahot badhiya content
@cburrito10004 жыл бұрын
nice list of videos. very useful and understandable
@anirudhkashyap53934 жыл бұрын
Could you explain the hold time constraints for the inverted clock case because I am getting it as tcq + tpd >= thold + tinv + T/2
@rambalaji7254 жыл бұрын
Me too
@rambalaji7254 жыл бұрын
Is it wrong in the video?
@aashnajain65193 жыл бұрын
Me too
@rohitgaykhe98833 жыл бұрын
me too
@tuongluongthanh20305 жыл бұрын
thank you for your presentation !
@GaneshPatil-vj1qp4 жыл бұрын
Too good explanation on this topic so far i have seen anywhere👌👏best👍Thank you😊
@HardwareNinja3 жыл бұрын
Hi Ganesh, check us out for engineering interview related questions. We'd love to hear your feedback! kzbin.info/door/7h3PROcX7Zgx00alQokJ-w
@shashikantsingh49935 жыл бұрын
good work bro...it is really helpful
@pavankumarreddy78885 жыл бұрын
I dont think there will be any hold time violation for the clock diagram for the case of inverted clock given to the 2nd FF becz.. Anyways data will be held constant by the 1st FF while 2nd FF is sampling the data if the Set- up time constraint is met.
@kalyan1576 жыл бұрын
Heyy you are excellent.Thanks a lot.Please do more
@electroTuts6 жыл бұрын
Thanks for your support Kalyan, will make more videos as soon as possible!
@gudipatiramu59846 жыл бұрын
I really liked the Inverter Question. But, detail explanation would be much more helpful.
@harshavardhanmittapalli56056 жыл бұрын
Hi, why in the inverted clock case setup time check is with respect to same clock edge (after all it can be seen as a delayed clock with clock skew equal to inverter delay plus T/2).why not with respect to next clock edge??
@electroTuts6 жыл бұрын
great question!! You can do in that way also, then you have to meet the setup constraint of the next clock edge and hold constraint of the same clock edge. Then, STC becomes tcq + tpd + tsetup = tinv + T/2 + thold Depending on the delays between the 2 flip flops, the case shown in the video or the case you have considered should be choosen. I hope that I answered your question!!
@harshavardhanmittapalli56056 жыл бұрын
Thanks for the reply @electroTuts. So it all depends upon the delay. But if we consider the case that was illustrated in the video then the output is available before the second clock cycle ( i mean before second edge occurs). We expect the output to be available after 2 clock cycles as we have 2 FF's. As it was the case in clock with out inverter.
@electroTuts6 жыл бұрын
Exactly !!
@harshavardhanmittapalli56056 жыл бұрын
So in that case the data that was available at the input of second FF is overwritten.
@manojharshavardhan23853 жыл бұрын
So basically in this case we consider the hold analysis for current clock edge and the setup analysis for the next clock edge.
@MichaelAaronBerger3 жыл бұрын
As everybody has stated, it should be tcq + tpd >= thold + tinv + T/2. since in his example, at -t/2 on rising edge is before the first flipflop even started.
@HardwareNinja3 жыл бұрын
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@priyasahoo42804 жыл бұрын
as I have studied hold violation doesn't depend on clock period but here in case of inverter we see it is depending on T. please clarify.
@akshaygehi114 жыл бұрын
I have the same question.
@HardwareNinja3 жыл бұрын
Hi Priya, check us out for engineering interview related questions. We'd love to hear your feedback! kzbin.info/door/7h3PROcX7Zgx00alQokJ-w
@007DARP6 жыл бұрын
I watched all your videos regarding Timing Analysis. In the second Video you did the analysis considering clock skew and in the third with buffer. Shouldn't the Static time analysis equation of both will be the same? Just like the Hold time Analysis. Because Clock Skew and Buffer both are adding the delay in the clock of the second Flipflop.
@vlsikr3 жыл бұрын
Nice. Setup-time Violation or Hold-Time Violation, which one is worse?
@HardwareNinja3 жыл бұрын
Hi, check us out for engineering interview related questions. We'd love to hear your feedback! kzbin.info/door/7h3PROcX7Zgx00alQokJ-w
@rohitgaykhe98833 жыл бұрын
explain once again the last HTC when inverter is added.
@RandomHubbb4 жыл бұрын
the content is great, thank you. but i have an unrelated question : I like your handwriting and the pen you are using. What brand and type of pen is that? i keep looking at the stores and could not find a similar tipped pen so far :)
@bitopantalukdar98205 жыл бұрын
The way you are holding the seems as if your index finger will break sir.....