ESD (PART - 2)

[@mistakesimake2012]

You guys are amazing and have not wasted even a single second of the viewer...Crisp and To the Point Videos

[@swathisareddy7069]

Hi, You are giving valueble information from basic level. Whenever i open ESD topic end up with so many doubts. but, now i got clear idea w.r.to circuit. Thank you for sharing this.

[@analoglayoutdesign2342]

thats the main intention of this channel...trying to touch upon basics....thanks for the feedback...

[@timegogo4182]

Dearest Sir, I wish I have a teacher like you when I was a high school student! Thank you so much for sharing your knowledge generously here, we are all your students 🙏

[@analoglayoutdesign2342]

Thanks for the feedback

[@vattypants]

Abe la*de, high school me ye sab nahi padhaya jata 🤣🤣🤣🤣🤣🤣

[@amjathhusain8605]

Excellent video..I couldn't get to see these concepts explained in the standard books available for IC design..Thank you so much!

[@analoglayoutdesign2342]

Thanks for the feedback

[@rounaksworld7106]

this is excellent explanation. Thanks a lot. I really loved it

[@khanhlinhle712]

Thank you for your work. It help me so much to understand ESD.

[@analoglayoutdesign2342]

Thanks for the feedback

[@tanluu1944]

Excellent ESD explanation. Thank you.

[@analoglayoutdesign2342]

Thanks for feedback

[@Sourav_Soumyajit]

Brilliantly composed and explained.

[@analoglayoutdesign2342]

thanks

[@raushanpandey7169]

Thank you very much sir for explaining the ESD concept from the basics. Once again thanks.

[@arun65394]

Thanks sir.. your clear explanation makes us to understand easily.

[@rajathmvenugopal8313]

Very well crafted video with plethora of information.

[@tranhuuthong07]

Great Professor, Thank you very much!

[@analoglayoutdesign2342]

Thanks for the feedback

[@abhisheknath1363]

Very happy with the explanations

[@ganeshtalupula9632]

Hi Sir, 1--The power clamp will be functional when the primary esd protection diodes is turned on right? 2--And is it requires the chip to be powered for esd discharging through clamp or without power also it will discharge? 3--- If there are different circuits to work in powered and non powered conditions can you please explain in detail... Thank you for your lectures and addressing all the queries🙏

[@analoglayoutdesign2342]

ESD occurs generally when a person touches the bare chip by hand.. other scenario is when a machine picks and places the IC on a pcb for soldering.. both cases power supply will not be connected.. just for understanding the thresholds, I used that vdd value..

[@ganeshtalupula9632]

@@analoglayoutdesign2342 got it sir...thank you

[@Blue73ocean]

Dear Sir, Thanks a lot for this excellent explanation!

[@cpradeepk]

hello thanks a lot for the video. it was very useful.. I have a comment, we can't have a back to back connected diodes between different power supplies, as the diodes will get turned on during normal operation. back to back connected diodes can be only connected between grounds.

[@analoglayoutdesign2342]

they will have. suppose vdd1=1.2V and vdd2=2.4. your point is, from 2.4 to 1.2V supply the diode gets f/w biased because of potential difference. They will put 3 diodes in series. so effectively it will turn on only when the supply is 1.2+0.6+0.6+.6=3V. not at mere 2.4volts only. Hope this clarifies.

[@cpradeepk]

@@analoglayoutdesign2342 hi yes.. we need to carefully put how much diodes in series we put depending on the vdd1 and vdd2 supply difference..

[@張鈞堯-h4m]

Nice Work~ Thank you for sharing these ideas~

[@ganeshbabutalupula4029]

Hi Sir, I felt i learnt many things from your videos...thank you so much for sharing knowledge in such a great manner. I have a doubt that what happens if we are turning the device on with power assume 5v and why the nmos device will not discharge the actual power supply as the esd device remains on chip and there is no enable to turn it off during power on...?

[@analoglayoutdesign2342]

During normal power ON we will not have esd type of supply.. suppose we have 5v supply maximum we will operate it is 5.5v…where as esd threshold will be little higher and in esd, the rate at which the supply increases is very very high

[@analoglayoutdesign2342]

Hope this answers

[@ganeshbabutalupula4029]

@@analoglayoutdesign2342 Sir does it means ESD nmos threshold voltage will be higher than the normal supply voltage?

[@analoglayoutdesign2342]

Please look into the pdk for esd devices and their characteristics.. in these videos, I have given high level overview of esd structures and their basic behaviour.. these kind of structures are used generally but not limited to only these.. it’s only qualitative analysis.. it’s not quantitative analysis…for exact behaviour you must get in touch with esd team..

[@ayushmantripathi5797]

I understand how back to back connected devices will protect circuit during an ESD event. However, when no ESD event is taking place won't back to back connected diodes, discharge the higher Vdd. For example: If Vdd2 = 5V and Vdd1 = 3.3 V, then ESD diode will always remain ON and large flow of current in static condition and eventually destroy the ESD diode. So this restricts the range of VDD's we can have. VDD2 shouldn't be greater than VDD1+0.7V and vice versa. Am I correct ? Thanks for the great content about ESD.

[@analoglayoutdesign2342]

Nice observation. In between 5v and 3.3V, they will not place 1diode... They will connect maybe 3 in series to match the voltage difference. Hope this answers ur question

[@ayushmantripathi5797]

@@analoglayoutdesign2342 Thanks a lot for your quick reply. It answers my query.

[@vinaymeneddi4308]

Hi , I have one question I think u may know this,that is about antenna diode,I searched but I didn't got exact answer, Question is how the charge get discharged in antenna diode? For that basically two diodes are their pdiode and n diode,in p diode basically 1st it is connected in reverse bias, for long length metal of gate during plasma etching that charge accumulated on that metal will get discharged by that diode(will become forward bias),but it is not working for ndiode ??? Please reply me,or I will give my number?

[@goldahong4392]

Dear sir, thank you for this video. I could not understand why do the ESD have to go through the Vdd then to the other end of circuit? Why not design ESD in such a way that it goes directly to the ground through the primary or the secondary protection? ( Am also confused why the diodes are designed such way forcing the current to flow through Vdd instead of go to the ground directly. ) Hope Prof you could enlighten on this. Thankful. 🥹🙏

[@analoglayoutdesign2342]

Please watch all the videos on esd. There are basically two schemes.. one vdd based protection and another is vss based protection. What ever you have watched is vdd based protection. In vss based protection, the discharge is to ground and not thru vdd.. Hope this answers

[@arnabsaha8531]

Very good videos!

[@tianzining]

Thank you sir! That’s all I want to say

[@babaktorabi313]

Hey Sir, for the power supply clamp, why do we assume a 0 to 5V increase during an ESD event? Wouldn't VDD have been at 5V prior? In this case, the voltage at the output of the RC circuit would not have started at 0 V?

[@analoglayoutdesign2342]

When ESD occurs, the chip is not powered..only substrate is at ground...that assumption is valid..vdd will not be connect to 5V....;..... when I say 5V, that will be the threshold that will be set for ESD event to be limited to...hope you got it..

[@babaktorabi313]

@@analoglayoutdesign2342 Hey Sir, so ideally during an ESD event when the chip is off, the circuitry will not see a voltage greater then 0.6v assuming that's when the diode is forward bias? The 5v example was just showing the threshold when the circuit was on?

[@babaktorabi313]

One more question, what if during operation, we get a huge voltage on the PAD. In that case, the output of the RC circuit will not be 0 so how will we get a power rail discharge?

[@venkateswarlugandrikala5655]

Always we assume the voltage/current is grounded! What will happen to the ground terminal? No potential difference there?

[@anilsn8219]

Thank you for such a nice video on ESD diode, i do have a question if there is a negative spike, how will the rc delay work in supply clamp?

[@analoglayoutdesign2342]

assume there is a negative spike, then the big mosfet is a bi-directional device...or symmetric device...so source and drain are interchangable... now the scene is gate is at zero and drain is at -ve voltage... Drain behaves like source and there is net vgs>vth...so the mofet turns on and discharges from ground to supply pin.. (which has -ve voltage)... this way we can understand....hope its clear..

[@anilsn8219]

@@analoglayoutdesign2342 Thank you for your quick response, i do have a another question, Lets assume the chip has been powered up, as chip has been powered up the VDD line has 5v, now the cap in rc has been charged, now if there is an positive ESD spike, as the cap is charged the o/p of inv is zero hence nmos is off, how will the extra rise in vdd line will be discharged through GND?

[@analoglayoutdesign2342]

@@anilsn8219 ESD events generally happen before powering up of the IC. when a person handles the IC the charge accumulated on him discharges thru the IC...thats why we have Human Body model...another type is while machine does the soldering....thats when we have the machine model etc.... when powered, we must have other methods of protection...

[@analoglayoutdesign2342]

@@anilsn8219 ESD events happen before powering up...when a person touches he discharges the charge..hence HBM... while machine handles the IC for soldering...Machine can discharge...hence Machine model...etc... after powering up, there must be other protection methods...

[@anilsn8219]

@@analoglayoutdesign2342 Suppose if there is a ESD event at VDD or GND pad itself, is still the combination of rc, inv and nmos clamp holds good?. If so can you please explain the discharge path sir

[@bheemanathiprasad2839]

Dear sir, thanks a lot for sharing topic ESD. I would like know one thing about when HBM occurs at IO PAD then the voltage is 2Kv . As discussed in the video for 7V , added secondary dual diode to protect the gate.. so how to protect the gate from 2KV in HBM

[@analoglayoutdesign2342]

I am not getting your question correctly... But if there is no discharge path, then the voltage will shoot up to to 2kv.... Moment the diode gets fw biased, it will limit the voltage to around 7v as in the case of example discussion... Hope I answered..

[@yogeshpalkar6078]

1) Why ESD is dissipated into supplies? Won't the supply rails get damaged? 2) What protects the input ESD diodes in case of long duration spikes? 3) The VDD protection that you talk about, the buffers will have their own delay to turn on the big NMOS. What happens to VDD during this delay when the NMOS is off?

[@analoglayoutdesign2342]

1. No there will be a supply clamp. That is meant to dissipate the ESD energy without voltages reaching higer values and damaging the devices. 2. ESD events are high energy events..but last for several 10s of nano seconds maximum.... if the duration of the spike is very high, surely the IC will get damaged. ESD devices are placed inside the IC based on the kind of ESD protection the IC needs. hope this answers.

[@yogeshpalkar6078]

@@analoglayoutdesign2342 what about 3rd question

[@analoglayoutdesign2342]

3. Sorry I didn't see that question... yes..RC delay +series of inverter buffers delay needs to be accounted in design. So the driver buffer will also be big and will be a tapered buffer... if this delay is more than designed, then esd will fail... the voltage will shoot up.. hope this answers

[@vizier_of_the_dead]

Hello sir, could you explain the working of the Power clamp in the normal supply conditions? Esp during the transient times. If we turn on normal supply, due to the RC constant, the input at the driver is low and the gate of the clamp NMOS sees high which turns it on. As a result, it sucks in the initial current from the supply. Is this the right behavior?

[@analoglayoutdesign2342]

Yes..power supply ramp up times are higher than esd ramp up times..so RC values and thresholds need to be selected accordingly

[@vizier_of_the_dead]

@@analoglayoutdesign2342 Thank you, I think I got what I need for my chip.

[@phanipasagada94]

Hi Sir, Not clear overall ESD protection circuit when you combine both primary connection + power supply rail protection. What is importance of inverter which is just after primary b2b diodes. Hope that is for signal and second one is for power. Can you pls clarify

[@analoglayoutdesign2342]

Hi, please go thru all esd videos again and again.. I have explained from very basics..

[@rscreepin]

I don't understand how back to back diodes work in multiple VDD scenario. Let's take a practical example, 1V8 and 3V3 supplies. Such configuration would draw a huge amount of DC current from the larger 3V3 supply towards 1V8 supply

[@analoglayoutdesign2342]

Between 1.8 and 3.6 we will not connect 1 diode.. suppose the vt of diode is 0.6v then three in series would make 1.8v between 3.6 and 1.8v

[@rscreepin]

@@analoglayoutdesign2342 I see, thanks for the quick answer

[@wish_one_knot5006]

22:15 vdd1 different from vdd2 obviously the back to back diodes needs to be off in normal operations how do we ensure that ?

[@analoglayoutdesign2342]

Yes true… if vdd1 and vdd2 are for eg 1.2 and 1.8v, then two diodes will be placed in series…assuming 0.6v threshold effectively it’s 1.2v.. hope this answers

[@MinhTriVo-vt8lc]

Thank you so much, I must login just to say this.

[@analoglayoutdesign2342]

Thanks for the feedback

[@Kalinaidu]

In power supply rail protection you take inverter but why you say buffers

[@analoglayoutdesign2342]

Buffer means that circuit which has high drivability.. it can be inverting buffer or non-inverting buffer.. hope this answers

[@ramann1547]

Could you show a demo how to simulate the IOPaDS ?

[@analoglayoutdesign2342]

What exactly are you looking at? ESD simulation?

[@ramann1547]

Consider , I have an IO pad and what all paramenter I need to check before signing it off ?

[@analoglayoutdesign2342]

Ok .. regarding analog circuit simulation, many are asking.. will figure out… need little time

[@sandip2130]

Thank you very much sir, this is the best explanation I found for ESD till now. But you have missed one event when VSS has positive spike wrt VDD. there should be one diode from VSS to VDD Please correct me if I'm wrong. Thank you.

[@analoglayoutdesign2342]

ya...that can be seen as a negative spike..

[@vimakuma]

What if VDD1 and VDD2 are not same voltage. ?

[@thinkbigakshayeklare9123]

Hello sir..I have not found video of driver..as you said we have done with driver..will you please tell me I which part we have completed?

[@analoglayoutdesign2342]

In ESD part3 its there I think...just check ..its also called tapered buffer...

[@vectorhehe1037]

For this chain of inverters, do they connect to the same VDD or other power supplies?

[@analoglayoutdesign2342]

During esd event, there wont be any power supply... During this time power supply clamps will act... And different power supplies will be connected using back to back diodes...

[@vectorhehe1037]

@@analoglayoutdesign2342 Thank you sir. Is there a lecture regarding PLL and VCO?

[@analoglayoutdesign2342]

Will upload video on vco next..in few weeks

[@pallavisingh9973]

please also make video on how to simulate in cadence

[@analoglayoutdesign2342]

I also want to do that actually

[@pallavisingh9973]

Please make🙏

[@hemantpise3414]

can you please explain about resistor value and diode size

[@hemantpise3414]

how we can decide the size diode which is connect to back to back

[@analoglayoutdesign2342]

Size of the diode depends on the current rating.....and ON resistance or forward drop.... foundry will provide info on this...

[@hemantpise3414]

Thank you so muchh

[@hemantpise3414]

Diode means diode so in which manner the size of diode increase

[@venkateswarlugandrikala5655]

Why we need secondary protection on only rx pads, not on tx pads

[@analoglayoutdesign2342]

tx pad is generally connected to drain of the circuit...Rx will be connected to gate of the circuit...

[@venkateswarlugandrikala5655]

@@analoglayoutdesign2342 thank you.

[@srikanthSrikanth-to7jh]

what is the use of back to back connected diodes, without that diodes we dc clamp the charge to ground

[@analoglayoutdesign2342]

I didn't get the question..sorry.. can you please elaborate...

[@analoglayoutdesign2342]

Sorry I didn't get the question... can you elaborate please

[@manishkumar-cn6ip]

Don't you think that, big nmos will not have 5v it will have the spike which can destroy the nmos gates. Please comment

[@analoglayoutdesign2342]

ESD devices are separate devices..appropriate time constants shall be designed...so that it will not increase the gate voltage...

[@BhaskarReddy-oc4cy]

Hi Sir , Could you please post lecture on drivers and pre drivers.

[@analoglayoutdesign2342]

Please check.ESD videos...info on drivers is present