ESD (PART - 3)

This video explains about Snap back devices, GGNMOS,GCNMOS, SCR, Substrate triggered GGNMOS. It explains the VI characteristic (vt1,It1), (Vh, Ih) & (Vt2, It2)

[@arun65394]

Thanks for the video which makes us to learn new techniques in depth.

[@analoglayoutdesign2342]

Snap Back devices are little tricky to understand. Hope it's clear..

[@Cutie_beauty_dujju]

crystal clear, to the point, and made easily digestible. Thank you for the valuable information.

[@analoglayoutdesign2342]

Thanks for the feedback

[@tianzining]

I’m working in the industry for decades. These lectures are diamonds! This is the first time I think I really learned something about analog design. No wonder Indian engineers like IC design army all over the world. You have very good teachers !

[@swathisareddy7069]

We got indepth analysis related to ESD . Thanks for providing these kind of videos.

[@analoglayoutdesign2342]

thanks for the feedback

[@krishnachaitanya6800]

Thanks a lot very detailed info on snap back which is very rare

[@Sourav_Soumyajit]

Thanks for sharing such useful videos. :)

[@336pratik]

Very detailed explaination. Thank you

[@analoglayoutdesign2342]

Thanks for the feedback

[@3RiversSQ]

Sir, why you stopped creating videos? Your way of teaching is ultimate. Or any other youtube channel or paid videos are thier?

[@analoglayoutdesign2342]

Thanks for the feedback.. only reason is I am quite busy with personal and official work.. hopefully I will resume in few weeks..

[@keshabdas298]

Sir, I have a doubt. Why the drain voltage is getting low in the snapback device and once again it is going slightly higher. Can you please clear my doubt?

[@analoglayoutdesign2342]

Hi, please go thru the video again and Again and pause in between.. that will help.. if you still didn’t get please msg me

[@localdude579]

With regards to the secondary protection, why do we need that? Why can't we just place a resistor right before the primary protection? That should reduce the ESD voltaga, innit ?

[@analoglayoutdesign2342]

Our primary aim is to make a way to remove the charge that is accumulated… the discharge path should have least resistance primarily.. that’s why resistance is avoided in primary path..

[@mohitupadhyay4866]

thanks for your intensive efforts. well, could you please tell us the source of these topics from where you are referring? thanks.

[@analoglayoutdesign2342]

There is no one source... I have collected info over period of 10yrs...after that I have demonstrated suitable circuits to comprehend easily.. that's all ...

[@Whatshappeningpeeps]

Could you please explain me what is the differences between supply clamps and power clamps? are both same? if not how they are different? i know supply clamp will protect the input lines or circuit by sending esd event to vdd using primary or secondary clamps and from vdd to gnd using ggnmos or BigFETs . Even power clamps will protect the power lines like whatever esd event is occurred or arrived it will send to gnd using either snapback or active devices. So now both are doing same sending esd event from vdd to gnd. then how to differentiate. Im not getting this. could you please help me to understand this?

[@analoglayoutdesign2342]

For what I understand both are Same..

[@rajathmvenugopal8313]

Thanks sir ,for this informative video

[@dhirajthalladi4934]

Thanks for the video I have a question . Why do we require power clamp for ggNmos protection as we are not clamping the ESD current to VDD ?

[@analoglayoutdesign2342]

GGnmos itself can be used as power supply protection.... GGNMOS will be used to protect the gate of the transistor of a signal coming from the input pad. it will not protect power supply rails if a esd event occurs...hope this answers

[@dhirajthalladi4934]

Thanks for your reply sir ,so you mean to say that ESD event can even occur on VDD rail and for its protection we need the ggNmos power clamp. am I right sir?

[@analoglayoutdesign2342]

yes

[@dhirajthalladi4934]

@@analoglayoutdesign2342 Thank you so much sir for ur reply. I have one more question please answer it sir. How the capacitor gets discharged in the RC triggered power clamp after the ESD event so that it can protect for another ESD event that may happen later?

[@analoglayoutdesign2342]

@@dhirajthalladi4934 Capacitor will also discharge thru the power supply clamp only. The power supply rail itself fall...so capacitor voltage will also fall..

[@vinaymeneddi4308]

Hi sir,I had a doubt ,if avalanche beakdown occurs mean that a huge Current will flow the the diode ,but after esd occurred their won't be any depletion region between n and p,so after esd occured,the actually signal that should pass the bump will also be grounded??? But it should not happen , then how? Please reply this question.

[@vinaymeneddi4308]

Please reply this ??? Any one

[@subasumala3138]

Thank you, Sir, for the video. Can you explain more on how the negative resistance region occurs?

[@analoglayoutdesign2342]

If voltage increases and current increases, then it's positive resistance... If voltage increases and current decreases, then it's negative resistance... that's what happens... Hope this clarifies... If you need further info, please let me know

[@suryaabinga3987]

@@analoglayoutdesign2342 Hi Sir, theoretically your above answer applies on the negative resistance region. But phenomenon what really happens inside the lateral NPN structure of the GGNMOS? electrons are swept across the drain junction and holes are swept across the substrate which might lead to a small substrate current. Similarly what really happens so that we are seeing the negative resistance region??

[@陳子軒-c7s]

​@@suryaabinga3987 He majored in I.C. design, not semiconductor device physics.

[@Gkcptplm]

Hi the SCR based structure is similar to LUP ,rt? Won't this form a short between anode to cathode as it is a positive feedback? this we cannot use for supply clamps too,rt?

[@analoglayoutdesign2342]

Hi, yes, they use SCR structures for ESD protection..including for power supply clamp. Here we discussed some of the structures. There is no limitation to that. I have made an effort to give a general understanding of ESD.

[@Gkcptplm]

@@analoglayoutdesign2342 Yes this is a very helpful video on ESD explanation ,thanks for your efforts . I was trying to understand what would happen if those SCRs get triggered due to supply/gnd bounce ? 2. in GGNMOS when we get a -ve PAD strike where does the charge discharges? as the drain -bulk is forward bias it wont discharge to gnd of GGNMOS,rt? Thanks for your time

[@analoglayoutdesign2342]

@@Gkcptplm 1.supply and gnd bounce will be lesser...around 100mv or so.. 2. if -ve spike comes...ggnmos gets fw biased and substrate will discharge

[@sivasankaransc3384]

Thank you, Please post more videos...

[@anilkumarpattapu7984]

How voltage decreases while current increases in ggnmos

[@bhanukallepalli2676]

Its really helpful. I didn't get one point.. In GGNMOS operation, How voltage vd is decreasing in negative resistance region.

[@analoglayoutdesign2342]

In the avalanche breakdown region, the voltage will decrease....

[@sudo7806]

Thanks

[@srikanthSrikanth-to7jh]

waiting for new videos sir

[@analoglayoutdesign2342]

Sorry for the delay..