DEEP N-WELL (DNW)

[@sisirmaity8356]

I enjoy your teaching

[@kavitareddy3349]

Nice explanation sir ...pls add still more vedios related to io layout

[@analoglayoutdesign2342]

Ok.thanks for feedback. Will do in sometime

[@ritubhagat7860]

good explanation, !st time i understand deep nwell so closely

[@sanjayreddy9035]

Thanks for posting useful video

[@varshakamat789]

Very Nicely Explained. But in lower technologies like 65nm or 45nm, we don't have this bottom isolation I.e Deep N well.. We isolate a device only from side by adding rings and use ASUB layer to clear LVS.. How does this not pose a problem in device operation ?

[@analoglayoutdesign2342]

There won't be any problem.. please watch agnd,dgnd,isolation video...I think I have explained this there

[@analoglayoutdesign2342]

They may short agnd, dgnd at pad level.. they may do a star connection there

[@98505177229850590818]

Excellent video

[@arunbrvce]

Hello sir. Good explanation. Just one question. What happens if I connect the bulk and source of the 2nd transistor together without deep nwell?

[@analoglayoutdesign2342]

Any Nmos transistor without DNW, bulk is at ground. So whichever transistor you short bulk with source, even source will be at ground.

[@vishalmanchanda4213]

just to add a point, the fabrication cost increases for deep n-well significantly so it is used in a very critical stage.

[@analoglayoutdesign2342]

DNW costs more..thats true.....one mask more....

[@sushantsharma180]

sir can you please make a separate video on that .Why we powered deepnwell to vdd and why not to vss

[@analoglayoutdesign2342]

ok sure

[@rajasekharnallamekala4950]

hi sushant , DNW is formed by a n well ring , the n well ring is connected to vdd so DNW is connected to vdd , the DEEP N WELL has the effect of decreasing the noise coupling through It to substrate and it isolates the nmos devices which can be at different potential from gnd.

[@TheWizeRabbit]

if you connect, deepnwell to vss, it can act as a forward biased diode with substrate. (n-p connected to vss). We must always make sure that parasitic diodes are reverse biased for non conduction :)

[@rajasekharnallamekala4950]

To isolate local sub and global substrate (p), We use deep n- well . By using dnwell VT doesn't vary then there is no body effect . Finally dnwell is used to avoid body effect .

[@analoglayoutdesign2342]

when you connect bulk to source then there would not be body effect. but DNW is not only used to overcome body effect. It will also provide isolation. Please watch video on AGND, DGND & ISOLATION.

[@rajasekharnallamekala4950]

@@analoglayoutdesign2342 ok sir

[@kandrashilpasree114]

Hello sir I saw all videos of yours which is very connected to me and please try to upload all second order effects.

[@analoglayoutdesign2342]

Sure..will do

[@varshakamat789]

Usually ,We connect Deep n well to highest potential ( say VDD =3 V) .. Is it possible to have a 5V PMOS device inside this Deep N well?

[@analoglayoutdesign2342]

Nwell and DNW will be inherently shorted. Whatever voltage you connect to nwell will be shorted to DNW also. When you connect 3v to nwell and 5v to dnw, then you are essentially shorting 5v and 3v with little higher resistance that's all...

[@narayanamurthig3315]

Sir is there any change of wpe and latchup by adding deep Nwell. Thanks sir.

[@analoglayoutdesign2342]

There is one video on latchup with dnw...check that

[@MALAYAPH24]

Awesome

[@neelimak3950]

Why mostly p substrate is used as globally substrate

[@analoglayoutdesign2342]

NMOS is faster transistor bcos of mobility. It needs psubstrate hence they use psub. Before cmos it was only NMOS transistors that were used.

[@ManojKumar-jw5ys]

thanks sir, but wt is mean by bulk?

[@analoglayoutdesign2342]

bulk means p-substrate for nmos and nwell for pmos

[@rajasekharnallamekala4950]

in which situation DNW is connected to gnd? again in which situation DNW is connected to vdd ?

[@analoglayoutdesign2342]

Dnw and n-well are shorted...so it should be connected to higher voltage...

[@analoglayoutdesign2342]

Not to ground

[@shwetakundgol6468]

Could you please post the videos on fabrication steps, WPE, LOD and body effect concepts.

[@analoglayoutdesign2342]

Sure...every week I will upload one video... I will surely upload all these

[@sharathseshadri3634]

why can't we use p+ in DNW

[@analoglayoutdesign2342]

Why du you want to use?

[@sharathseshadri3634]

I want to know what happens