GATE Solved Problems (2011) | Sequential Circuits | Digital Electronics

[@maheshmahesh-rl1yb]

sir upload practice questions on sequential circuits..

[@JatinKumar-ve9km]

SIr can u plz upload videos of Asynchronous Sequential Logic(Analysis procedure,circuit with latches,design procedure,circuit with latches,reduction of state and flow table,race free state assignment)

[@hemasundar3514]

please post remaining videos of sequential circuits and also the registers and counters

[@mridupabantalukdar]

Wow! That's a great explanation 🙏🙏🙏

[@sureshbhati1692]

Thanks to you solving this confusing question

[@franctiekam3008]

Sir please I don’t understand why you said the input of Qb is the complement of the previous data Why is it so please?

[@engineeringandlife3181]

How the input of A flip flop os even avaible before the completion of clock pulse that is D1. Please help me explain and why u didnt took previous data to be 1

[@firdoshkhan3713]

thank u very much for ur video pls make a video on IC 7490 in a way how can it be used to make mod 6, divided by 75 etc

[@surajbhushan3596]

sir needed lectures on feedback amplifier

[@sohamkulkarni19]

Can you please add videos of new questions this playlist is 7 years old

[@soniasimran5426]

You can Google and get all previous years questions

[@Kshitij19971]

Hats off to you :)

[@chillarigesai1385]

Thank you sir..

[@vaibhavimishra763]

sir pls upload gate problems on counter so that it will be crystal clear to us

[@pawan_wagh]

Sir please upload also analog electronics gate problem video

[@gauravtomar4204]

Sir plz upload more questions on sequential circuits

[@krish-ei4hp]

sir pls post abt asynchronous sequential circuits

[@Vigei]

why it cant be present data 0 and previous data 1?

[@nirmalkumar-ff3cl]

PLEASE UPLOAD THE VDO OF LOGIC FAMILY PLS SIR

[@soniasimran5426]

Please Solve the gate 2003 4th question with details explanation boolean expression reduction

[@franctiekam3008]

Please where can I get those gate questions ?

[@mnnr9310]

where did u find the questions from?

[@kanthakborkar7845]

Sir .. plz add more problems

[@fullmotion1913]

HEY I NEED A HELP to design synchronous sequential network that has one input i1, one output o1, a reset signal r and a clock Clk. The output becomes 1 after the completion of the input sequence xxxxxx (. The circuit can be realized using the D flip-flop with reset (DFFR). Reset signal r to be connected with the reset input in the D flip-flops as to allow their initialization. The circuit should be from Muro type, which means that the current output of the circuit should not depend on the current input, and in fulfillment of the sequence should be gone in a special situation which shows output 1, and then from there accordingly should continue any of the other conditions without losing any entry

[@techarena5813]

sir please upload fet lectures

[@thought1430]

Sir concept hil gya...

[@ABHisheKSHarma-cd1cf]

send ur link of Facebook id

[@realshiva_0206]

Thank you sir