Getting Started with an nRF52 Series MCU Part One

If you've been wanting to dive into the massively popular nRF52 microcontroller, this is the perfect video for you. Tech Consultant Zach Peterson explores a custom design to show you exactly how to get started with the nRF52 in Altium Designer.
0:00 Intro
0:36 Getting Started with the nRF52
2:15 The Circuitry
4:24 Creating the PCB
6:18 Layer Count
11:10 Vias and Pads
For More Getting Started with an nRF52 Series MCU videos, click here: • Getting Started with a...
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For more Tech Consultant Zach Peterson
videos, click here: • Technical Consultant Z...
👉 Watch the Entire nRF52 Series: • Getting Started with a...
👉 Which BGA Pad and Fanout Strategy is Right for Your PCB: resources.altium.com/p/which-...
👉 How to Design Automatic Fanouts for BGAs in Altium Designer: • How to Design Automati...
👉 When to Use Via in Pad: • When to Use Via in Pad
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[@Zachariah-Peterson]

Hi everyone, I'll share the finalized files for download after the 4th video in this series is released, I'll also post them in the description for this video.

[@joncedarleaf]

I also hate adding rooms! Quick way to disable that: Project > Project Options > ECO Generation tab > Add Rooms - mark "Ignore Differences" instead of "Generate Change Orders" > hit OK.

[@Zachariah-Peterson]

It would be cool if it would just stay disabled when you un-check it in the ECO dialog

[@gabrielruiz1467]

The learning content you guys provide is astounding. RF and high speed is one of the most interesting topics in hardware design for sure. Hope to meet you in person someday!

[@AltiumAcademy]

Our pleasure!

[@illesbalog]

Hi Zach, is there any reason why you went with the BGA Package instead of the QFN? I'm asking because i can find the QFN for much cheaper.

[@Zachariah-Peterson]

Mostly because we wanted to do an example with a BGA instead of the QFN. I've also used the BGA in multiple projects and had it manufactured, so the example here shows how to deal with the HDI aspects of this particular package.

[@illesbalog2]

@@Zachariah-Peterson Thanks for the reply. But I can also go with the QFN and there won't be any significant differences?

[@Zachariah-Peterson]

@@illesbalog2 in terms of the device capabilities and interfaces, no there is no difference. The BGA component is more useful in the case where you are already doing an HDI stackup build and you will be using blind/buried vias anyways, so you might as well use the BGA. In a conventional build, you could not use the BGA unless you have access to very fine line etching capabilities and no larger than 6 mil drilling, and you might not comply with IPC Class 2 requirements. In conventional builds you can always use a different package.

[@DannyBokma]

This is so cool! Thanks for sharing / making this!

[@AltiumAcademy]

Glad you liked it!

[@leeslevin7602]

This content is brilliant, thank you so much for sharing.

[@AltiumAcademy]

Thanks for watching!

[@davidgmos]

Very helpful tutorial, the only thing is that 6 layer PCB with blind vias is too expensive. QFN package options is the way to go for a lot of projects

[@Niels_Dn]

What is that transistor circuit on the power rail?

[@nulldev42]

It looks like a means for temporarily measuring the supply/battery voltage. It's temporary so it doesn't put a constant drain on the battery.

[@mostafanfs]

High quality material as always!

[@AltiumAcademy]

Glad you think so!

[@sanjikaneki6226]

Is there also going to be a series on the NRF91xxx ? ( the ones with GSM and GNSS )

[@Zachariah-Peterson]

Good idea, looks like I will need to put this together, should be a fun design!

[@sanjikaneki6226]

@@Zachariah-Peterson NICE BTW surprised that i get a reply at this time , YT comment magic u never know when u get a reply !

[@Zachariah-Peterson]

@@sanjikaneki6226 I have been backed up on answering comments but I'm trying to get through all of them today!

[@midhunvr7236]

Good video

[@douggale5962]

0.5pF? So, 500 femto farad then? How is that even a thing? Won't you have so much parasitic capacitance, that it doesn't do anything? How much parasitic capacitance would there be in that region of the circuit? Down in the femto farad?

[@Zachariah-Peterson]

Great question, the parasitic capacitance with ground on the next layer could be a significant fraction of the capacitance and that would modify the cutoff frequency for the matching network, which is one reason to use a ground cutout below that transmission line going into the antenna (we'll see this in part 4). It is still a coplanar line so the GND on the top layer sets the impedance, and there is GND on the bottom layer, so that significantly reduces parasitic capacitance. I'd like to note that if you calculate what the cutoff frequency is for that circuit, it's already much higher than the edge of the RF band (the band ends around 2.5 GHz), so a little bit of extra capacitance around that pad (from fringing and the cutout) won't greatly change the circuit behavior. Also your tolerances in that capacitor could be larger than the leftover parasitic capcaitance with the cutout (depending on the stackup).

[@TheEdmaster87]

This could have been done with just 4 layers

[@Zachariah-Peterson]

You probably could, depending on where you are routing you could still get the required isolation between signals with ground. This actually brings up a really good topic about layer reduction, which we sometimes have to do in order to optimize a design before scaling, so maybe I'll make a video on that topic!

[@TheEdmaster87]

@@Zachariah-Peterson Wouldn't be bad at all. I have made a 4 layer board with this mcu. 1-4 feed-thru via and 1-2 hidden via.

[@Zachariah-Peterson]

@@TheEdmaster87 Filming it tomorrow, stay tuned!