How to draw timing diagram for D Flip flop with asynchronous inputs(Preset & Clear) ?

[@moneymagic8679]

Finally a good explaination. Thanks!

[@KarthikVippala]

Ahhh finally a good support💪. Thanks for watching 🙏

[@peteyiu]

Hi Sir, thanks for the video. you started attacking the problem by working on active low. Is it active low because as in 1:59, as long as an input is low, the output is high (nature of NAND gate)?

[@komakulaharikanth2057]

Super explanation bro

[@KarthikVippala]

Thank you bro , good luck, good health 👍

[@f.m986]

Greet very helpful

[@KarthikVippala]

Thank you 🙏

[@makumarrr385]

Small doubt the circuit which u hav explained is that active low r active high preset clear inputs???

[@janvipatel7022]

Hey, so if it’s prst always output will be one, and in clr always we have to do zero?? Like everytime ?

[@davideyaliscool]

Thanks for the explanation

[@KarthikVippala]

Namaste 🙏 smnsdndn dhs, your welcome, good luck & great health 👍😊

[@lovely_ji]

Your videos are good, but Why are you using lot of fake accent, just be normal man, we all live in India, it's nothing shame in talking in indian accent. Just be normal talk normal, hindi is also fine.

[@KarthikVippala]

Namaskaram Akshay Kumar 🙏, it's just that I get confidence in this accent somehow😉, I am improving on my accent please check latest videos , jai hind👍, good luck & great health 😊