Handshake synchronizer (clock domain crossing)

Hey guys in this video I have discussed about handshake synchronizer, with timing diagrams for illustration ,
Thanks for watching the video .
please do subscribe it will help me a lot

[@boliu9984]

Thank you so much! I have been struggled with this problem for about one month. You totally saved my life!!!🥰

[@KarthikVippala]

Happy to help!

[@sriharikumargoud]

All most all CDC doubts are clear to me. Thanks for the videos Karthik..

[@DmitryS-fu7kv]

DATA lines and REQ line can be routed in FPGA in very different paths and lengths. Thats why synchronization work only for one signal - REQ. If you want synchronize DATA, you need "set max delay" between REQ path and all DATA paths (REQ to DATA0, REQ to DATA1 and so on) to less then one clock cycle (of maximal clock).

[@sunnyyou6169]

Super brother nice topic

[@manlupiano1431]

Nice explanation Karthik. Just double check, this handshake synchronizer can be applied on both CLKA > CLKB and CLKA < CLKB right?

[@anilkadiyala]

First of all Great work. I support u in making great videos like this !!! As explained pin-pointed 3:40. After metastability, it(A1Q) would go to a stable high but that is not always guaranteed. Right ??. pessimistically it may settle to low also. which I consider that as bad luck and the whole functionality will ruin. please give ur views.

[@matteoserva8648]

Thank you for that video

[@KarthikVippala]

Thanks for the support 🙏

[@MrVerilog]

One thing not made clear is that when the sender receives the ack it needs to set the request signal low because the receiver needs to be waiting and watching for it to go low so that it knows when to deassert it's ack signal.

[@nabhay583]

I don't get it, so the sender doesn't change the data as long as REQ is high and ACK is low, once the receiver gets the data ACK goes high and the sender sees this. After receiving the ACK the sender makes REQ go low? If that's how it happens then how is the next bit sent? Shouldn't REQ be stable for the next bit also?

[@rishikumar.n.g.5854]

Hi Karthick.we are going for N stage synchronisers to fix CDC.How is N calculated?

[@pranavgupta4552]

Hi Karthik What is the drawback of handshake CDC technique , which motivate us to move to FIFO syncronizers.

[@varunmajji6514]

Might doubt is after metastability it might go to zero also right

[@a.v.varunraj2141]

Can u draw the timing diagram for passing multiple signals....

[@seejingyin998]

Can we use handshaking method when passing signal from high frequency clock domain to low frequency clock domain (usually use asynchronous FIFO) ? Or is it only applicable from low frequency clock domain to high frequency clock domain just like any other synchronisers (two flipflops) did?

[@KarthikVippala]

Hi see Jing yin, thanks for asking the question, Yes we can use it for high to low . Good luck, good health 👍

[@zenithchokshi9365]

Hello Karthik, How receiver gets to know that all the data bits were received or not?

[@sandhyaramasubramanian2375]

Thank you for your amazing videos 🙂 1. Why the metastability of the data is not a concern in the handshake method? 2. Why is it that you mention metastability in A1Q but not in B1Q?

[@sandhyaramasubramanian2375]

Please could you reply to my doubt?

[@KarthikVippala]

Hey sandhya , thanks for asking the question, metastability can still occur in handshake synchronizer but here we able to send data more than single bit. Metastability can occur at B1Q , but for the example I have taken req is coming at time where there is no violation , at A1Q there is violation so metastability is shown . This is just a scenario , while working it can be different. Good luck, good health 👍😊

[@swapnilmittal8002]

Hi.. Great video.. Just one doubt.. In the video, A1Q is going high on the same cycle as ACK. But shouldn't it be delayed by one clock cycle.?

[@KarthikVippala]

Namaskaram Swapnil , Two clocks are different Ack is arriving just before the clock edge of clk A so A1Q looks it is sync with Ack , my drawing is not that clear ,you can try on paper for better understanding , Good luck & Great Health _/\_ , Take care:)

[@mounikaathuluri7196]

Good video...very informative Can u do any video on how to keep timing constraints related to FPGAs.....pls

[@KarthikVippala]

Hey mounika , thanks for asking. Do you mean create clock, input delay , output delay. If my understanding is wrong , please elaborate the topics 👍

[@mounikaathuluri7196]

@@KarthikVippala Yes exactly...its all about sdc constraints

[@KarthikVippala]

Ok I will make it but I will make it in July 1st week

[@mounikaathuluri7196]

Thanks

[@saloniraj7564]

Why can the data not be changed until it recieves ACK signal? Could you please clarify this? If the data is changed after one cycle, even then it could be stable right after it passes through 2 flop synchroniser? Then why is this constraint passed that it should not be changed?

[@ranjanparnami]

Thanks

[@KarthikVippala]

Welcome

[@ranjanparnami]

@@KarthikVippala Nice to hear from you. do you have any link/ video/ notes/ article on basic operation/ theory of ADC , their types, worming, selection criteria and interview questions. Please let me know.

[@bennguyen1313]

When there is slow logic that needs to catch a pulse generated by fast logic.. what are the alternatives to the handshake approach? ( Sender outputs data and THEN asserts REQ Receiver latches data and THEN asserts ACK Sender deasserts REQ, will not reassert it until ACK deasserts Receiver sees REQ deasserted, deasserts ACK when ready to continue ) For example, is there a way the pulse could be stretched, such that to guarantee it would be seen by logic running from the slower-clock?

[@arpitgoel885]

Hi whats the difference between handshake based pulse synchronizer and simple handshake synchronizer

[@oscarcastilla3217]

Hey man great video, I only have one question, how would it be the adaptation to vhdl code?

[@KarthikVippala]

Namaste 🙏 Oscar , will add two flop syn in code by using always block. Thanks for asking good luck and great health 👍😊

[@oscarcastilla3217]

@@KarthikVippala Thanks man!! New sub here

[@KarthikVippala]

Grateful 🙏😊

[@agarwalchucky]

Shall depth of flops used for synchronisation should be same for data transfer control and ack ? If no, then how it is decided ?

[@KarthikVippala]

Hey Chakra , thanks for asking the question, Yes it can vary , we must choose depth such that we don't get metastable state , for data transfer it we may require 2 , for ack we may require 3 , it all depends on the clocks. Good luck, good health 👍

[@agarwalchucky]

@@KarthikVippala Thanks... I was also thinking of that... It would have been to include this in your video and what is the best way to identify whether your synchronization with ack is functionally correct or not ?

[@KarthikVippala]

@@agarwalchucky I missed that , I will answer the queries if you have any.👍

[@anilkadiyala]

@@KarthikVippala I heard this method designed in such a way of irrespective of clock ratios. And coming to question raised by Agarwal ji. Its all depends on the MTBF. And inturn MTBF is inversely proportional to incoming data rate.

[@uday5786]

Thank u so much

[@KarthikVippala]

Your welcome 👍. Hey do you need any other topics ,so that I can make a video

[@uday5786]

@@KarthikVippala mux synchronisation

[@KarthikVippala]

I will do that ,any other than synchronization 👍

[@uday5786]

PLL

[@KarthikVippala]

@@uday5786 ok I will 👍

[@saurabhsrivastava2370]

What is the resource you use to make these videos? I want to solve practice problems

[@KarthikVippala]

Hey Saurabh thanks for asking, I have found these on papers published on synchronization, you can search it on web for it. Good luck 👍

[@saurabhsrivastava2370]

@@KarthikVippala Thanks a lot. Can you make videos on Lockup Latch Concept?

[@KarthikVippala]

Hey Saurabh thanks for asking, Yes I will make it , can tell me what you need

[@saurabhsrivastava2370]

@@KarthikVippala I never got the timing considerations using Lockup Latch correctly, so it will be great if you can explain it.

[@KarthikVippala]

@@saurabhsrivastava2370 hey I will try to it by next week , is that ok for you👍

[@apoorvupadhyay7669]

please share one example code

[@KarthikVippala]

Namaste 🙏 apoorv , thanks for asking,Sure will do it upcoming video, good luck and great health 👍😊

[@bhuvskaya8898]

@@KarthikVippala where is the. Code?

[@KarthikVippala]

@@bhuvskaya8898 no video on code

[@bhuvskaya8898]

@@KarthikVippala do u have any document or text file of code?

[@KarthikVippala]

No

[@naveenagarwal2651]

Sirf A1Q should be delayed by 1Tclk wrt ACK right? You've shown both in the same clock edge