Latch-up in CMOS Technology | Latch-up Formation & Triggering | Issues in Physical Design

[@krishnakittu6637]

Very Good lecture. easily can understand if one knows operation of diode well

[@TeamVLSI]

Thanks Krishna.

[@dheerajroyal5561]

Very good explanation..! Sir

[@TeamVLSI]

Thanks for liking Dheeraj. Keep watching for lots of such available tutorials and many to come. Keep supporting the channel.

[@sb6701]

Can you please add this point when u uploading a video to prevent latchup -“how latch up is prevented by adding tap cells on core with particular distance.”

[@TeamVLSI]

Thank you Bindu for your valuable suggestion. I have already planned to cover at least two latch up prevention techniques, tap cells and guard ring. Thanks you again for right suggestion at right moment. I will try to address you concern.

[@Santoshkumar-lw1gf]

Sir in video u have connected body p+ and body n+ to Vss n vdd respectively thn how does lactup occur still??..since to avoid latch up v r using well tap which gives same vdd n Vss connections.

[@TeamVLSI]

Hi Santosh, Thanks for raising a very good point. I would like to say in this regard, Well taping is a way to prevent Latch-up, and well taping in nothing but connecting N+ well and P+ Substrate to VDD and VSS respectively. But in this example, I have tried to establish that there is such connection but these are not sufficient enough that's why emitter-base junction of parasitic BJT gets forward biased. If the well is sufficiently tapped, the drop to the base ( which is in well) will not be high enough to make for emitter-base junction forward biased (cross the barrier potential). Thanks.

[@Santoshkumar-lw1gf]

@@TeamVLSI thanks a lot sir ur reply helpd.. and i hav found ur videos vry useful sir... Thy stand apart from rest of KZbin VLSI videos plz keep uploading more content sir.. thanks a l Ton sir __/\__

[@prateeksharaikar7273]

hey!! Can you make a video on scan chain??

[@raviraju1450]

Excellent work sir. From you only i understand this topic very well.Thank you sir . Can you put any pdf for this? 👏👏👏👏👏

[@TeamVLSI]

Thank you.

[@sameernandagave749]

Awesome

[@TeamVLSI]

Thanks Sameer. Happy learning!

[@snkhy5631]

thank you sir

[@rahultheytv5347]

Thank you so much sir

[@TeamVLSI]

You are welcome. :)

[@sohamdas7775]

WhatsApp group given in description is full . Do you have any other WhatsApp group ?

[@TeamVLSI]

Yes we have started a new group recently.

[@TeamVLSI]

chat.whatsapp.com/C6etLHR6oAf6G9bLGDwdOf

[@sohamdas7775]

@@TeamVLSI Thank you!! I am a beginner in this field, currently pursuing Mtech in VLSI 1st year Any tips, suggestions or advice for me .

[@TeamVLSI]

Be connected with us, and ask doubts in group.

[@sohamdas7775]

@@TeamVLSI Thank You .

[@SUYASHAGRAWAL-j7c]

I don't know why but I still did not understand despite my sincerest efforts.....

[@karthikram3161]

Explanations are not good, pls improve ,not understand what you are saying.

[@TeamVLSI]

Ok Karthik. I will try my best. By the way where do you feel difficulty to understand? If any particular point, you can discuss. :)

[@anamsrinivas6674]

at triggering mechanism sir

[@pavangudipati6]

Thank you so much sir

[@TeamVLSI]

You are welcome @pa1