Memory Chip Organization Part 1 - Georgia Tech - HPCA: Part 4

[@sugiramadhas5119]

Thank you so much. Can you explain the working of 16 bit memory chip with 1T1D DRAM

[@FaraAziz]

Very effective explanation! thank you...

[@lanchanoinguyen2914]

but why ram 62256 is 9 rows address and 6 columns address so the data matrix would be 81x36=2916 bits while the datasheet says it's 512x512=262144 bits.can you explain?

[@shashankrao4443]

Row address is 9bits = 2^9 = 512 Col address is 6bits = 2^6 = 64 Hence, addressable memory cell = 512 * 64 = 32768 Columns are typically read in a burst of 8 bits. So, your actual bits = 32768*8 = 262144bits

[@lanchanoinguyen2914]

shashank rao i have been thinking about what you said but still don't understand it. 2 terminal means that 4 possibilities and 9 terminal means 81 example: 01;10;00;11 so what to do with 2^9 ? it should be 9^2?

[@t07minas]

@@lanchanoinguyen2914 u have 2 possible bits per bit cell so s^9, its everytime 2^x , x=something

[@xiaodongzhao2741]

it is really a good sharing. thanks

[@aspire8999]

Thankyu so much sir

[@tumtum6910]

U have invisible pen! OwO