🔥Power Dissipation in CMOS || Himanshu Agarwal || Digital Design for Campus Placements

[@HimanshuAgarwal_]

Correction at 45:55 - The output will be stable at Vdd/2, not predictable. ( Considering kn=kp) Try thinking about PMOS NMOS current. You will understand it

[@chiranjibdatta9245]

Bhaiya aap itne acche videos banate ho...apme dosto ko suggest krne mekn darr lagta hain...kahi unka jyada score na aa jaye tests mein!!😞

[@MuhammedJasim-h7w]

Thank you very much for making such informative videos sir. This was a concept I tried so painfully hard to learn. May god bless you❤

[@42pardumangupta14]

As know the inductor does not allow a sudden change in the current similarly cap also does not allow a sudden change in voltage so vout going 5v to 0v so voltage is slightly up to compensate the sudden change in voltage similarly happens when vout goes 0v to 5v voltage is slightly down to compensate the sudden change in voltage . I thought this will be another explanation....

[@ckam-o6l]

sir, you said that by decreasing vdd vih also deacreses similarly voh also decreases right ?? how there is trade off in noise margin As NMH=VOH-VIH