QFN Layout and Routing - Tips & Tricks

QFN (quad-flat no-lead) packages and their surrounding components can be difficult to lay out and route on a PCB, due to their small size and narrow pitch. Learn how to make QFN design easy with Altium Designer, featuring Philip Salmony, Tech Consultant for Altium and the mind behind Phil's Lab.
00:00 Introduction
00:46 QFN Overview
01:57 Example: USB Hub IC
03:29 QFN Package Examination
04:30 Board Stack-Up and Controlled Impedance
05:59 Layout
07:04 Decoupling Method #1 (Not preferred)
09:08 Decoupling Method #2
10:06 Decoupling Method #3 (Preferred, double-sided)
12:37 Routing, EP Vias
14:37 Outro
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[@wyattr7982]

Im a big fan of both this channel and Phil’s Lab so this is awesome. I hope we get plenty more Phil on this channel

[@PhilsLab]

Thank you, Wyatt - definitely more videos to come! :)

[@chaitanyasindagi1237]

@AltiumAcademy Your loop isn't that large in your first decoupling capacitor layout example and I would venture to say that it's the best option here for two reasons 1. The ground plane that is 0.09mm away is where the current will go through, it won't go to the bottom layer so the loop area is more like 3*0.09=0.27sqmm. Compared to having it on the other side which would give you a best case loop area even with ViP of 1*1.6= 1.6sqmm 2. Vias have added inductance which is probably a similar magnitude or even higher than the loop area we looked at above. The short via length to layer 2 will have much lower inductance than a long one all the way to the bottom layer. Layout guidelines for decoupling caps of GaN MOSFETs often call out this discrepancy in the layout technique used by many power electronics engineers because the rule of thumb about opposite side is better only really made sense back when boards were 2 layer only. I don't have a way to prove this in simulation since I don't have access to a 3d field solver, but if someone does, I'd be most appreciative of their contribution to this comment I also fail to see how the added ground via next to the 3V3 via on the last example will make a difference to the via inductance since there won't be any significant return current through that via. An extra via isn't really going to help there

[@NathanSweet]

Since this isn't answered, it makes me question all the information in this video.

[@michaelcummings7246]

With the ground vias the current spreads out over a much bigger area and causes crosstalk. Can't remember the channel name but the host have professor on that shows 3d view of the voltages and current with and without them in a simulation and they make a huge difference for the ringing as the current tries to find a return path. Basically the current stops spread as soon as it hits ground via vs traveling 5-10 farther without. So instead of no current through it like you stated almost all of it goes through it.

[@chaitanyasindagi1237]

​@@michaelcummings7246this is absolutely true for high speed signals that are changing layers. You need to connect the reference planes of the starting layer to the ending layer with a via/cap to allow the ground currents a short and low inductance path back to the signal source. However that's not the case here, we're decoupling a power pin and already have a via going from ground on the capacitor to ground on the IC, adding a ground via further away from everything doesn't improve inductance because the return current is flowing through the capacitor and to the closest via, not the one on the other side of the capacitor

[@brightpan9219]

I‘m sorry to ask but why the via 9:30 is placed between the QNF-3.3V pad and Cap?

[@____sammy____]

Genius layout idea. I love this man

[@AltiumAcademy]

Glad you like it!

[@TheLemon22]

Hi Phil! Excellent video. I have one comment. At 9:20 in the video you discuss putting the pair of vias close to the QFN IC pins and then placing the capacitor below them. This is actually less ideal from a de-coupling perspective - ideally you have your capacitor pads as close to the IC pads as possible, placing the pair of vias below the capacitor. This gives you the lowest overall loop impedance due to the lower impedance loop generated between the IC pads and the capacitor itself (low impedance at high freq) EDIT: The exception to this rule can occur when you have a really massive PWR plane well coupled to GND - in that example, your plane actually acts as a much better low-impedance loop path for your de-coupling and your initial placement of the vias is therefore correct

[@PhilsLab]

Thanks! Indeed - it's all a compromise. Placing the cap on the bottom will have a larger loop inductance, however gives you much more freedom when routing out the IC. I've never had problems with this method (for Gig Ethernet PHYs, USB PHYs, MCUs, etc.) - so this is my preferred method (I believe Robert Feranec also prefers this).

[@TheLemon22]

@@PhilsLab thanks for your reply! What I was referring to though was the positioning of the vias at 9:20 in the video. The order should ideally be via pair --> capacitor --> IC pin pair instead of capacitor --> via pair --> IC pin pair as you've demonstrated I do love your method of placing the capacitors on the opposite side of the PCB though and I am probably going to start doing this myself. Thanks!

[@DaleMitchell1367]

@@PhilsLab really, Robert Feranec prefers this? All the videos I've seen from him involving decoupling capacitors, he places the capacitor as close as possible to the IC, not the vias as close as possible to the IC.

[@TheDigital19]

whaaat Phil got recruited by Altium? love it!

[@jonnymakers9560]

Excellent!!

[@scottpelletier1370]

Definitely trying the ground via adjacent to power via with caps on the bottom side on my next spin. Thanks!

[@EfraAv]

This is brilliant, Phil. Thank you!!

[@jeffweinberg4906]

Absolutely brilliant! Excellent advice and techniques.

[@PhilsLab]

Thanks, Jeff!

[@TheEuzikial]

Thank you Phill. Great video!

[@erinmutchler3612]

Super helpful! I'm working on a RP2040 microcontroller and this will help immensely with routing!

[@PhilsLab]

Thanks, Erin - hope all goes well with your RP2040 design. I do have a video covering RP2040 hardware design using Altium Designer, in case you're interested: kzbin.info/www/bejne/jmGTdKBrgbKBh80

[@erinmutchler3612]

@@PhilsLab I've watched this video several times! Super helpful as well :)

[@PhilsLab]

@@erinmutchler3612 Glad to hear that! :)

[@bartek153]

Great vid Phil. Cheers

[@sergeysamolin]

Amazing video! Thaks you! I learned a lot of useful things for my work

[@AltiumAcademy]

You're very welcome!

[@PhilsLab]

Thanks, Sergey!

[@pcbworks]

Wow! I'm so surprised to see Phil here. Greetings!

[@AltiumAcademy]

Hello there!

[@flippro8989]

Thank you so much! It work!

[@AltiumAcademy]

Glad it helped!

[@exapod23]

I always found QFN easier to solder than high pin count TQFP. Double sided placement is better for the loop but not for manufacuring cost. Regarding method 2 isn't better to place the via before the cap? So the current flows: via -> capacitor -> pad?

[@HuescaYGOTCG]

¡Excellent video, @Phil's Lab and @Altium Academy! However, I have a doubt: What about IC ground pins? Must they be connected through one via to GND or do they have to be floating? Could you explain to me why, please? Thank you so much!

[@wimbuh1]

Hi Phills, big fans

[@PhilsLab]

Thanks, Dimas!

[@PhilsLab]

Thanks, Dimas!

[@ahsanalirafaq805]

can you make a video onwhat thickness of pcb traces to keep for high speed pcb traces as well as normal traces.

[@santoshadate1426]

I wasn't lost until he said "Control + Zed" instead of "Control + Z"

[@SABARI-nv9kf]

Sir , how to select the value of capacitors and resistor for a circuit

[@0xbenedikt]

Helpful video, but I don’t really like going for a double sided load if not absolutely required

[@Andrew-dp5kf]

Why are you putting that extra ground via next to the +3.3 via? It’s not totally clear to me. You mentioned briefly “improves inductance” ?

[@viggstable305]

Would you recommend placing Decoupling for QFN on bottom of 8 layer board ? stack up would be S-G-P-S-S-P-G-S

[@antiprosynthesis]

What is your opinion on having a 4-layer stack-up like this? L1: Power L2: Signal L3: Ground L4: Signal + SMD The logic behind this stack-up is that I'm constrained in size and can't reasonably combine the traces on L1 and L2 on a single layer, and I want to keep the signal as close to Ground as possible.

[@xehpuk]

Nobody better qualified answered so here are some thoughts. One argument for signals on top an bottom is in case you made a mistake and need to do some patching, top an bottom vias can be cut. Other then that I guess the substrate is thickest in the middle so not very much is gained by your suggested stack up. Perhaps it is noticably better on a small and very thin PCB. If you have a lot of current then top and bottom layers can usually handle more current.

[@vonnikon]

That thinn sliver of soldermask between the QFN pads will not be possible to manufacture. Should be removed completely, or adjusted to a manufacturable size. It will be a tradeoff against the soldermask registration. Keeping soldermask between QFN pads can help reduce solder bridges.

[@remy-]

7:40 this stepped down trace, can this be done by AD?

[@PhilsLab]

You can use the teardrop tool (built-in to AD) for example.

[@saumyacow4435]

Given the difficulties and cost (and potential quality control issues) of having surface mount components on both sides, I'd treat this as a last resort.

[@Zachariah-Peterson]

Placement and assembly of SMD parts on both sides of a PCB is a non-issue unless you have overlapping BGAs in an HDI board. Sometimes that might require multiple reflow passes on a single side of the board. For QFNs it is not a problem.

[@NguyenTam-zl2tk]

Very helpful! I am a beginner. Please show me how to draw a descending size route from Vcc supply to Vcc pin. Thank you very much.

[@PhilsLab]

Thanks - I'd suggest using Altium Designer's teardrop tool for that.

[@estefannysaucedopena850]

perfect speed 1.25

[@remontlive]

7:40 how did you route 3 size trace, can someone explain with more details? How to do that?

[@vzwGrey]

In Altium, while drawing a trace you can change the width by pressing the TAB key. This "pauses" the layout view and lets you access the properties panel while in the middle of routing a trace. In the properties panel you can change the trace width incrementally to achieve the effect in the video. To sum up: draw a segment of the trace with one width, increase the width and then draw the next segment. You can watch Phil do it in more detail in a video on his own channel: kzbin.info/www/bejne/hn6ooYSQbpWZaZY. The relevant section is a 1h57m30s in that video.

[@remontlive]

@@vzwGrey Many thanks for the detailed answer! You saved me a million years of searching!!! In addition, I already tried a couple of times to find the answer and did not find it. It seemed to me in the video that this is an automatic function, so I could not find it. Thank you very much again!

[@miguelperez1926]

Muy fan, una pena que no se ingles

[@NguyenTam-zl2tk]

Hi

[@miguelperez1926]

Hello

[@jonnymakers9560]

glad to see ONLY signal layers. Altium does a shitty job when it comes to planes...you cannot route on them...every other ecad tool I have used lets you route on plane layers...Not Altium

[@Zachariah-Peterson]

Well that is what makes it a plane by definition. But anyways you can route on a SIG layer with fill and then you can still export a Gerber for that layer in negative as if it were a plane layer, no one will know the difference.