Razavi Electronics 1, Lec 39, Biasing Techniques, Intro. to Common-Gate Stage

[@theminertom11551]

Professor, you can't possibly know how much I have learned from your class even after having done a lot of this type of work for almost 40 years. Thank You!

[@wagsman9999]

Everything is explained so clearly. Master teacher.

[@bassamsleiman-i5q]

greetings and special thanks from lebanon .. master 2 in microwave engineering physics

[@prasantnair1590]

Top class teaching, I loved it.

[@Sourav_Soumyajit]

Superb explanation!

[@stefano.a]

51:33 If the voltage on the drain is equal to the one of the gate, what value we have to select for RF? Thank you.

[@electronics_enthusiast]

More importantly, if there is no current flowing through Rf, then why do we need that resistor in first place. If drain and gate are supposed to be equal, then just short circuit them with a wire

[@alirostami9447]

thank you very much

[@shanthoshkumarm6873]

in 48:51 why no current flows through gate ?

[@amitjangra6833]

due to the SiO2 layer current will not pass through the Gate of MOS at low frequency.

[@baalakrishhnach3574]

As the MOS device to be in saturation Vds should be always greater than Vgs by one threshold. But at 52:00 we see that in self biased CS stage drain and gate are at same voltage as source is grounded we then have Vgs=Vds. Then the device will not be in saturation. But here it is mentioned as the device in saturation. Any one please help me that whether my statement is correct or not ??

[@prannoyroy8753]

if Vds=Vgs then obviously Vds>Vgs-Vth Substitute some values to understand this

[@vijayakumarr3519]

condition for saturation is Vds>Vgs-Vth not just Vds>Vgs. So if Vds=Vgs and if you minus one Vth from Vgs it will be always less than Vds so device will be always in saturation mode.

[@Hariharan_KA]

its not ' Vds should be always greater than Vgs by one threshold' its ' Vds should not be less than Vgs by one threshold '

[@oskarjung6738]

51:43 VSauce?😂

[@electronics_enthusiast]

Tf 😂

[@hajiclub]

We are adding degenerative resistor to the source that reduce the effect of variation in Id. But our signal which we are providing at the gate ass the small change, also acts as a variation in Id. So, would'nt this source resistor attenuates our information signal as well?

[@AliGhafoor92]

It does attenuate. Thats why gain of Source degenerated CS amplifier is lower than that of non-degenerated one

[@adityatripathi02]

The information signal that you are referring to is applied to the gate(VG). The drain current is sensitive to VGS(the difference between gate and source voltage) which does not change as much due to the degeneration resistor in the source. This is because VS(source voltage) goes up as VG(gate voltage/information signal) goes up, trying to maintain a relatively constant VGS.

[@zinhaboussi]

Id is depended on VGS wich is the difference between VG and VS not VG as value

[@himanshupatra1991]

At 58:20 while calculating Av(Vout/Vin).In Calculation of Vx/Vin why V1&V2 weren't taken into consideration ?

[@ayshaabdulgani442]

you mean R1 and R2?

[@MegaShaggy94]

R1 & R2 are just used to set the value of Vin, since we're calculating Vout/Vin, since the value of Vin is already set, we don't take R1 & R2 into consideration

[@anandsreekumar6687]

In earlier class, R1 and R2 were considered to derive the "attenuation factor" of a real system where Rmic is present. In this example Rmic can be assumed to be 0. Thus applying to the attentuation factor (R1 || R2)/ ((R1 || R2) + Rmic), the (R1 || R2) cancel each other if there is no Rmic. Thus we can ignore effect of attenuation due to voltage divider bias in this example.

[@Mouli-og2dk]

yes it should be counted@@anandsreekumar6687

[@anupammathur17]

@@anandsreekumar6687thanks for explanation!

[@DM1114-wd9rs]

in self based cs stage how Vg equal to Vd when there is a resistor between. and why will no current flow through it

[@sakshisingh4197]

Since no current no voltage drop so vg=vd and no current flows because there is a Capacitance between gate and substrate or you can say due to oxide layer which acts as insulator so no current flows

[@AkhoJohn]

❤

[@jobaerrashidkhan6412]

51:45 why?? Too suspicious🙂

[@mrpossible5696]

37:34

[@mrpossible5696]

43:00

[@MeatCreater]

33:39 Hopeless

[@gevorggeghamyan1718]

Thank you a lot