RF Design in the PCB: Transmission lines (coplanar)

High frequency signals are carried on circuit boards via transmission lines. Learn the differences between standard 50 ohm impedance microstrip lines and coplanar transmission lines in this video. We also explore the best-use cases for coplanar transmission lines, how they impact loss and interference, dielectric thicknesses, and more.
0:00 Intro
0:25 Coplanar Losses and Interference
0:41 Pinouts and Coplanar Transmission Lines
0:49 Large Dielectric Thicknesses
1:30 Altium Designer, Ground Polygons, Stitching Vias, & Polygon Pour
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[@rfengr00]

CPWG can have more dispersion and loss than microstrip. It all depends on the geometry and dielectric. The example shows two shunt components. The return currents on the coplanar ground are perturbed by the components.

[@questy44]

would you isolate the upper ground planes from the shunt components and connect them trough via's to the lower plane?

[@domtom128]

Great video as always! Did you add those cutouts under the components in the RF path manually or is s there a way to add them automatically?

[@Zachariah-Peterson]

Cutouts always have to be added manually unless there is some feature I am not aware of. The other way to do it is to apply a clearance rule only for the RF net.

[@BMM66666]

How long the minimum pitches of each via hole?

[@maleehakhalid3235]

Can we rely on ADS line calculator tool width calculation of cpwg track. For 16 GHz a cpwg track of 1.5 mm came as a result and I had to tapper when connecting the track in my circuit

[@MegaMindyLou]

How did you get the shielding vias to direct connect?

[@Zachariah-Peterson]

You can set up the default connection style in the design rules to be direct connect, by default it will apply to all pads/vias. I think also in the Add Shielding to Net dialog there is an option to set up a thermal relief if you did not already set it up in the design rules.

[@TheLemon22]

Can Altium address the bug with clearance DRCs and CPWG structures? If you set up clearance rules (GND polygon pour to 50Ohm track rule, for example) the actual clearance as the polygon pours adjacent to the trace, it is never perfectly accurate. You always (no matter what) have to adjust your DRC rule by the offset Altium creates, it's very frustrating and has been this way for many version.

[@Zachariah-Peterson]

I understand, I solve this either with a cutout as shown in the video, or with a specific net spacing rule between the coplanar net and GND. It would be nice if that part of the impedance profile could be auto-applied in the rules and constraints editor.

[@TheLemon22]

@@Zachariah-Peterson Hi Zach - just wanted to let you know that setting the Arc Approximation in the GND polygon to a really low value (we did 0.0001mm) will fix this bug