Setup Hold time of a Flip Flop | Why does a Flip Flop requires setup and Hold time

[@shashikantsingh4993]

its good explanation , but if you had drawn the waveforms for Q1 and Q2 also it would have been much better to visualize it completely, btw thank you...nyc work

[@TechnicalBytes]

True, aggreed

[@bobo_for_all]

Very nicely explained sir, I have never understand the word latch in Thanks for the that door explanation. You're example are easy to memorize Thanks for this video.

[@TechnicalBytes]

I am very glad to know that Videos are helpful to you.. I have created a complete Playlist on FLip FLops and latches .. You can go through it. Link is given below: kzbin.info/aero/PLPmSCnkkX4qvMfSrFZ70uXzUxmSdjU84c Please share your valuable feedback on them .. I am sure, these videos will open up your mind..

[@bobo_for_all]

@@TechnicalBytes sure Thanks for this

[@ecerahuljain]

Awesome explanation ! Plz Continue to make more video

[@TechnicalBytes]

Thanks Rahul, i will keep posting new videos.. please keep commenting :) :)

[@Agigeorge1984]

wonderful explanation..thank you so much

[@TechnicalBytes]

Thanks for your appreciation

[@AVINASHKUMAR-yd1gp]

So, The flip flop here is +ve Edge and the Latches inside are negative and Positive level triggered. Please confirm if I am correct

[@harshpreetsingh1228]

Amazing explanation, thank you so much

[@TechnicalBytes]

You are welcome!

[@sunilht1990]

Thank you so much for this video.

[@TechnicalBytes]

You are so welcome!

[@harshverma3399]

thank you, sir : )

[@TechnicalBytes]

Thank you so much Harsh for your comment.

[@helpslabsocial916]

NIce explanation .. carry on

[@TechnicalBytes]

Thanks for your inspirational words'

[@AVINASHKUMAR-yd1gp]

I have lost u after 12:16, why would Latch 1 with Negative level triggering pass D1 to Q1 after 1sec of Postive edge and in positive clock

[@viveksikarwar1884]

Sir ji Can you re upload this explanation again As you described setup and hold in latch in very great manner. But in this that is not so much clear. If possible please do asap

[@venkatvish9039]

Nice explanation!!!

[@joshuam8863]

thank you!

[@TechnicalBytes]

Most welcome !!

[@TejSingh-nh1uf]

Very nice

[@TechnicalBytes]

Thanks

[@vikasgupta1665]

Hi Sir, I have one doubt. when we are calculating hold time then are we not considering propagation delay in the circuit?

[@TechnicalBytes]

If you ensure that value is applied to flip flop before setup time, that means it reached to the output of first latch safely during level 0 of clock. Right? When positive edge comes I.e. level 1 of clock comes, latch 2 will start passing its input value (which is nothing but output of first latch) to its output. It will reach at output equal to 2nd latch delay. So, you can name second latch delay equal to flip flop propagation time, right? But when positive level of latch starts, because of not gate latch 1 is still active, it can corrupt its output, so during that time we need to hold input value I.e called hold time, right?

[@shivamporwal149]

very nicely explained!!!!!

[@TechnicalBytes]

Thank you 🙂

[@pennapatipavankalyan9567]

Thank u so much, sir. This is really helpful.

[@TechnicalBytes]

Happy to help

[@muhammadibnwahid6405]

Very well explained, thank you. May Allah have mercy upon you.

[@TechnicalBytes]

thank you so much !!

[@manojkumar-oe6fs]

Sir,how come when the clock goes high and D changes within 1ns then Q1 changes? Because D will be propagated to Q1 only after 2ns right.. Please clarify.. Thanks in advance

[@AVINASHKUMAR-yd1gp]

If u got the answer please reply back, i have got the very same doubt after understanding what he meant to say. Thanks

[@sandysandy6883]

Hi! Yes to change the Q1 completely it needs 2ns sec but it can go into metastability state or unknown value so to keep the stable value at Q1 we cant change D within a 1ns window

[@piyushnag6482]

@@sandysandy6883 i think the question he was asking that even if it changes within 1ns if flip flop output is taking 2ns to change we cant say for sure whether that change will reflect in the output or not because flipflop is getting inactive meanwhile after 1ns

[@yadukrishanankrishnakumar3072]

Awesome explanation..

[@TechnicalBytes]

Glad you liked it

[@sunilht1990]

Can you please give idea on CDC from interview perspective. I mean on what condition what kind of cdc solution is required. whether it 2 stage, 3 stage, handshake or FIFO. I have been asked this question by on of TOP company for Senior RTL engineer position.

[@TechnicalBytes]

Sure dear, I am going to start a new series of videos on CDC design.

[@TechnicalBytes]

Dear, upon your suggestion I started a new series of videos on CDC. First Part: kzbin.info/www/bejne/bXXSiISem9t0qrM

[@divyakumarshah2498]

Please make more videos

[@TechnicalBytes]

Thanks and surely put more effort to meet your expectations

[@rakeshreddy1365]

sir is masterslave flip flop pulse or edge triggered

[@ayushgemini]

master slave config is always edge triggered

[@ranveerdhawan5187]

Sir can you make a video on difference between latch and a flip flop , here in starting of video the output of latch and flip flop is shown to be different as latch is working as level triggered and flip flop as edge trigerred , but I have read that a latch is without a clock and a Latch with clock is called Flip flop , please tell if I am wrong. Havenot reached the correct answer of difference between a Latch and a Flip Flop yet , please share your knowledge sir

[@TechnicalBytes]

Dear Ranvir, we have created a dedicated playlist on flip flop and latches .. I am sharing link here.. please go through it .. and let us know your valuable feedback.

[@TechnicalBytes]

Flip flop and latches playlist: kzbin.info/aero/PLPmSCnkkX4qvMfSrFZ70uXzUxmSdjU84c

[@ashishsontakke4040]

I'm here in 2020 July

[@TechnicalBytes]

I could not understand you comment

[@pavankalyanlakkireddy4358]

due to so many adds your content did not reach people try to decreease adds

[@AVINASHKUMAR-yd1gp]

Don't mind but the explanation is a little confusing for a begginer, Please make a short script-type structure to avoid confusing sentences. Thank You for your efforts

[@user-gz6fr8xe6l]

tsao

[@TechnicalBytes]

Thanks !!

[@tejinderkumar4344]

Very nice

[@TechnicalBytes]

Thanks