Clock Latency in VLSI | Source Latency | Network Latency | Insertion Delay

[@debarunsaha8485]

Network latency is the delay from the clock definition point (create_clock) to the clock pin of a flip-flop. Source latency, also called insertion delay, is the delay from the clock source to the clock definition point. Source latency could represent either on-chip or off-chip latency. One important distinction to observe between source and network latency is that once a clock tree is built for a design, the network latency can be ignored (assuming set_propagated_clock command is specified). However, the source latency remains even after the clock tree is built. The network latency is an estimate of the delay of the clock tree prior to clock tree synthesis. After clock tree synthesis, the total clock latency from clock source to a clock pin of a flip-flop is the source latency plus the actual delay of the clock tree from the clock definition point to the flip-flop.

[@guongmomo3290]

How about set_clock_latency with -min and -max option?

[@UjjwalKumar-gl3rr]

💖💖

[@suprajithhs5609]

Excellent video ! I have a question related to this topic. Why do we use reference clock (instead of using only the clocks available in the design)in some designs ? Could you please clarify ?

[@TeamVLSI]

Hi Suprajith, A low frequency reference clock is required for PLL to generate the high frequency clock which is used inside the ASIC.

[@vaishnavip302]

Why Network latency is called as insertion delay???

[@jovysanchez398]

Hello! I would like to ask what will happen if we do not declare network latency in the SDC file. [1] How would the tool calculate insertion delay? [2] Is our goal to keep insertion delay as short as possible?

[@TeamVLSI]

Hi Jovy, In case of latency in not declared either in sdc file or in ccopt spec file, Tool will try to achieved the minimum latency. [1] Once the clock tree in routed, tool will extract the exact net and cell delay of the clock path and from that tool gets exact insertion delay. [2] Yes, one of our CTS goal is to achieve the minimal insertion delay.

[@jovysanchez398]

@@TeamVLSI Thank you for answering! This really helped clear things up for me.

[@manupotisreenivasulu401]

Hai sir,,,,this is cnu. I have small dout in insertion delay,,,,,source latency is also called insertion delay i think sir,,,,,,,this line I read in Vijay Bhasker test book,,,,, but you mentioned network latency is also called insertion delay sir,,,,,which one is correct sir.

[@TeamVLSI]

Hi CNU, Thanks for asking this doubt. I was actually waiting for this doubt. Initially I also had the same doubt. I believes network delay is the Insertion delay but when I referred the textbook of J Bhaskar I found in this book that it is stating that source latency is the insertion delay. Then I talked with the experienced STA guy and also referred some tool documentation and finally I found that the word insertion delay is used for network latency.

[@manupotisreenivasulu401]

@@TeamVLSI Thank you sir,,,,,,,I got it.