Basics of Clock Signal | Characteristics of Clock | Property of Digital Clock

[@manojaa8338]

Nice explanation

[@TeamVLSI]

Thanks for liking! Keep watching, keep learning!

[@padmajmanore8886]

Could you tell me the reasons behind the variations in duty cycle? Like why don't we get exact 50-50 pulse width?why there is ratio of 20-80?

[@pavankumarVilasagar]

Please explain about Min-Period violations

[@TeamVLSI]

Hi Pavan, Sure that will be covered on other video.

[@levonrostomyan8251]

I think that leading or trailing edges don't depend on negative or positive edges. it depend which will be first clock transition. if the first transition goes from high to low , the leading edge will be from high to low and the trailing edge would be form low to high, or if the first transiton goes form low to high it would be leading and trailing edge will be form high to low.

[@TeamVLSI]

So what is the reference of calling first clock?

[@levonrostomyan8251]

@@TeamVLSI sorry but i dont understand question. can you clarify

[@mekalagowthami162]

Pluse width variation,how it will effect and on which factors it will effect...? Plz give clarity on this sir..

[@UjjwalKumar-gl3rr]

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