sta lec30 clock gating checks part-1 | Static Timing Analysis tutorial | VLSI

[@kedharguhan]

Very critical video! Thank you.

[@truptichauhan3634]

Nice explaination

[@vivekgupta-qj2sy]

Great job👍

[@prakhargoel1962]

2:50 the clkB is being used as a clock for a flip flop below, isn't this being used as a clk downstream? If not, then what does it mean by being used as clock downstream? i am confused sir pls explain

[@kingwhite6418]

By downstream, he means the same clock driving the fanout logic of the gating cell (AND gate in this ex). The CLKB is not driving any of the 2 fanout flops downstream.

[@hitanshuvibhute1489]

for active high signal check if both A and B will be high at same time, B will be propagated to flipflop. but you said that for active high A should be changing from 0 to 1 while B should stay low I didnt get that point.

[@abdelrahmanmostafa2344]

In the Phase shift of 90 degrees case, why it is not considered like a positive skew (clock has a fixed delay) and setup is analyzed at next clk edge T required = Tclk - Tsetup + Skew (0.25*Tclk)

[@vinayakchoubisa9051]

First you said if the gating signal is clock then i lt can't be used as clock downstream but in next example you used clock as a gating signal and that is being used as downstream, what does it mean that ??

[@hardikjain-brb]

such useless playlist even confused me more better to read a book or blogs on sta

[@hardikjain-brb]

what is clk downstream

[@VLSIAcademyhub]

Clock downstream means, clock down the path until it reaches sink pin

[@vinayakchoubisa9051]

At 3.11 you said gating pin then and clka is going in gating pin but next you said clkb is gating signal what you want to say make it clear

[@NENOShorts]

true. other videos too he has made same mistakes

[@anirudhabehera5716]

5 and 0

[@shubhrajyoti3150]

Binod