Glitch Free Clock Mux | Clock Mux | VLSI | What is Glitch Free Mux | GFCM | Circuit

[@Electronicspedia]

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[@docvedios1955]

Simply outstanding, got perfect picture on the topic. Thanks a lot

[@harshitha-8256]

I found the video extremely useful for my interview preparation, Thank you!

[@vivekchin2]

Clk2 gets disabled in 1.5 cycles after sel value is changed from 0->1, and then it waits for 1.5 cycle of CLK1 to send it to output of the mux (rightmost OR gate) Last flops are kept at half cycle path. This is because when we are disabling one clock and switching to other clock this switchover falls in at the downtime of any clock, stopping all possibilities of glitch to occur, which otherwise possible only if CLK is @ high level. Its even more fun for 3x1 CLKMUX

[@arlenalem]

Thanks a lot for the video, it is really illustrating. Is there any book about this advance technics for FPGA?

[@oviya.n1317]

We can use negedge triggered flipflop for the the circuit responsible for generating enable . This will not chop the signal while stopping and switching to one clk from another. Crt me if i am wrong

[@AdityasTV]

Hi sir, can you explain how the flops D11,12,21,22 are reset (initially zero), and impact / metastability if any, when bringing the flops out of reset, and activating the clock mux. Assuming we are using async resets for the four flops.

[@Electronicspedia]

Hi, During reset phase all the four asynchronous resets will be asserted and all the four flops will have reset value of 0, At this time the clock will be disabled so we don't see the clock output. Only after the reset phase is done the clocks will be enabled. By this way we don't see metastability issue. Important thing to note is we need to have the two stage synchronizers for select signal to ensure we don't see metastability if select is asynchronous to input clocks.

[@AdityasTV]

@@Electronicspedia Hi sir, thanks for the response. However, won't the clock inputs clk1 and clk2 will be free-running? Or are you saying from system perspective, clock inputs clk1 and clk2 will be ungated/made available to system, after reset is released. Agreed about the reason for using 2flop synch instead of 1 (in place of D11, D21) ; I think its for this very reason; while the output of AND gate will be stable by the time the first flop samples it, but it wil provide guard against asynch data transition from 0 -> 1 for d-ff (2nd stage) once it comes out of reset (asynchronously).

[@Electronicspedia]

@@AdityasTV Clocks can be controlled or can be free running. But at a system level usually the clocks will be controlled / gated in order to overcome these issues of metastability and also to save power.

[@saravanavilashini1563]

It will be nice if u explain in verilog code also

[@Manikumar-gt9ov]

great content and explanation

[@EvgenyCeed]

Hi! How to apply the correct constraint for a clock formed in this way? The clock source must be declared on the output pin of this circuit?

[@AliMuhammad-sm9hx]

Thanks for the class. can you please also cover fsm design

[@sathishmitta6124]

We are getting the no lock window for some duration right, doesn't it effect the functionality of the design? Suppose if I required to get the mux output is continuous without no clock window with the clk1 and clk2 are same frequency ,sources are different. is it possible please clarify.

[@Electronicspedia]

Hi, two clock sources will be considered as asynchronous clocks. For such clocks you need GFCM. Having no output clock is absolutely fine for few clock cycles.

[@manojs5891]

Module ab ( Input a,s, Output y); Always@(*) If(s) Y=a end What will be the Circuit for these sir...

[@Electronicspedia]

It will be a mux with 's' as select line. Input I0 will be connected to output and I1 connected to 'a' input.

[@mustafanasser3132]

sir , i can't get why we put a negative edge ff you say safely sample the data but if we put +ve edge we still safely sample also

[@Electronicspedia]

If we sample the enable signal at an active high level of clock then we might see glitch because we have AND gate immediately after latch, Here the idea is to sample the enable when clock is not present and then AND with clock