Modelling of Memory Part-3| Modelling Synchronous FIFO|Verilog|Part 26

[@dheerajchumble5602]

Excellent tutorial. Such a clarity in thoughts. Each and every step explained very properly. Thank you sir.

[@hosseinrostami7708]

The code is well explained and working like a charm. Really time saving. thanks for sharing.

[@susanthawijesinghe5429]

Very nice description. It's very helpful to me. Love to see this kind of works more.

[@chetanbadagandi8789]

sir your videos are very helpful and have great explanation, sir please make video on asynchronous fifo also like this, it would be very helpful

[@johnkurian5869]

Very good tutorial. The code listing shows two counters fifoDataCount and dataCounter to keep track of no of bytes in FIFO. One of them is redundant?

[@parthsomkuwar2785]

Very informative Sir.. I request Modelling of DDR1/2/3 also Please.

[@Vipinkmenon]

We will never buld ddr memory inside fpga. There is no need of it and there is no point in it. There will be ddr outside FPGA which will be controlled by a ddr controller inside fpga (usually mig ip from Xilinx). So we may need ddr model during simulation. DDR manufacturers (like micron) provide the models for free. Of course they won't be synthesizable but only functional model. Even when u use mig ip core, Xilinx will also provide an example design with ddr model. That model will be also provided by the corresponding manufacturers. Modeling all timing behaviours of ddr (like precharge, auto refresh etc) are not easy. So better to use models from vendors.

[@parthsomkuwar2785]

@@VipinkmenonThanks for the reply and information, Sir !

[@AmitKumar-wf1qq]

Please Could you suggest where I will get theory of synchronous FIFO? Any book or paper?

[@Manishpundir04]

how to do for async fifo ?

[@dheerajchumble5602]

Sir please guide me on this issue. I am trying APB master code. Getting error in port declaration itself. Not getting how to solve. ///////////// Design Code: ///////////////////// module APB_NEW( input pclk, input prst, output reg [3:0]paddr, output reg [7:0]pwdata, output pwrite, output psel, output reg penable, input [7:0]prdata, input pready ); reg [3:0] addr_bus; reg [7:0] data_bus; reg [7:0] mem [0:255]; integer i; always@(posedge pclk) begin if(prst) begin paddr = 0; pwdata = 0; end else begin //if(psel)begin penable = 1; if(pready)begin if (pwrite)begin paddr = addr_bus; pwdata = data_bus; end else begin mem[paddr] = prdata; end end //end end end ////// Test Bench Code /////////// module tb_apb_new(); reg pclk; reg prst; wire [3:0]paddr; wire [7:0]pwdata; wire pwrite; wire psel; reg penable; wire [7:0]prdata; reg pready; reg [3:0] addr_bus; reg [7:0] data_bus; reg [7:0] mem [0:255]; integer i; APB_NEW dut(pclk,prst,paddr,pwdata,pwrite,psel,penable,prdata,pready); initial begin pclk = 0; forever #5 pclk = ~pclk; end initial begin for(i=0;i

[@varunsharma3860]

@Dheeraj Chumble Hi, Why are you driving 'pwrite' in your testbench? You've declared it as an output.

[@kisrisri8471]

Have you implemented this on FPGA board?

[@dheerajchumble5602]

@@kisrisri8471 no..I did not