Modelling of Memory Part-1| Modelling Random Access Memory (RAM)|Verilog| Part 24

[@Saikumar-kb4lf]

The best video for ram designing so far

[@ShivamSingh-wf2bd]

Best explanation I have ever found!

[@wafinirsaliah428]

can i get the testbench code

[@dainiusjaraminas6412]

simple ram testbench code version below>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> `timescale 1ns / 1ps module ram_tb; reg clk, wrEn; reg[3:0] wrAddr; reg[7:0] wrData; reg[3:0] rdAddr; wire[7:0] rdData; ram UUT(.clk(clk), .wrEn(wrEn), .wrAddr(wrAddr), .rdAddr(rdAddr), .wrData(wrData), .rdData(rdData)); initial begin clk=1'b1; forever #10 clk =~clk; end initial begin //write data to RAM wrData = 8'h01; wrAddr =3'd0; wrEn=1'b1; #100 wrData = 8'h02; wrAddr =3'd01; #100 wrData = 8'h03; wrAddr =3'd02; #100 //read data from RAM rdAddr =3'd0; wrEn=1'b0; #100 rdAddr =3'd1; #100 rdAddr =3'd2; #100; end endmodule