Antenna Effect in VLSI - English Version

This video contain Antenna Effect in VLSI in English, for basic Electronics & VLSI engineers.as per my knowledge i shared the details in English.
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[@SubhashKumar9844066820]

I watched your all Antenna effect lectures. it is really good ,easy to undestand and clear.

[@youthcentral493]

Sir sir I am also going to to VLSI physical design I was very interested so so I know for English knowledge verilog so you very helpful for this video sir

[@davet11]

You were quite terse to someone who questioned your copper versus aluminum metalization assumptions. You used the antenna ratio calculation for copper and then went on to say that we didn't have to worry about antenna rules for copper! For aluminum, the antenna ratio is calculated using (W + L) * 2 * Thickness / (Wgate * Lgate) because the top surface is protected by resist. I think you got your copper versus aluminum calculations mixed up. There seemed to be a lot of hand waving and talking about implanting metal (?) but perhaps this should clarify..... In an aluminum-based process, charge accumulation occurs during the ETCH step. The top of the metal is protected by a resist during this step, so the antenna rules for this process should be based on the metal sidewall area. In copper-base technologies, charge accumulation occurs during CMP (Chemical-Mechanical Polishing). In this process, the sides of the metal are protected, so the antenna rules need to be based on the metal's top surface area.

[@analoglayout]

Aluminum is fabricated in a different way , copper is fabricated in a different way , i mean the way of forming the metel over the silicon , so both the metal having antenna ratio , but compare to aluminum , copper have less chances of antenna because of the fabrication method , and also copper wil be used for top metal in most of the time , it's also another reason , top later fabrication is totally different method from bottom layer

[@rohanyadala9096]

Very good explanation. Super..

[@analoglayout]

Thx for Ur support

[@prasadpaturu9841]

Lecture is very clear and easy to understand, please help us to post Latchup video.

[@milindgoel405]

Just one error at 9:10 . The calculation seems wrong. It should (205x0.09)/(0.09*0.2) and not 200

[@neevarpgp]

Excellent Channel !

[@zazu9833]

@Analog Layout, I have some doubts: 1> @1:46 , you said that the charge is positive charge and not negative charge. Plasma definition says that it have positive ions and electrons in equal numbers, so how only positive ions come on metal? Also metal don't have ions right?, they have free electrons. Please clarify. 2> @29:15 , you said that in Cu process you are not using photo-lithography. I think that is totally incorrect! You need photo-lithography to know where the trenches will be made. Correct me if i am wrong. Thanks for the video sir. :-)

[@analoglayout]

First read the fabricate process of Aluminium and copper , then u will come to know who's wrong , and also read plasma etching working process , and plasma chamber operations also ...

[@zazu9833]

@@analoglayout Clearly what i have written in the 2> point is correct sir.

[@ikrutheking]

Antenna effect occurs as a result of Reactive ion etching, which will induce a charge in metal layer which will inturn transfer to polysilicon. For higher metal we use Dual Damascene process which will not result in inducing of charge. Dual Damascene process ofcourse contains photolithography and etching process. Al is not used in fabrication nowadays. Tungsten is first layer and Cu is the higher layer. For reference www.iue.tuwien.ac.at/phd/orio/node10.html

[@zazu9833]

@@ikrutheking Hi, I dont think dual damascene include cu etching. etching of cu is a huge chemistry problem for fabs, thats why they use damascene or dual damascene pocess.

[@sanketp20]

This is very informative video. I Appreciate your work. Thank you ! Just subscribed, left a comment and clicked the bell 🔔 icon 🤗

[@Army.indo7]

Drain connection also one of prevention in antenna

[@analoglayout]

Not possible

[@Army.indo7]

@@analoglayout we can see whether it's a floating metal and it is near by area we can connect.most of the time not possible

[@surendharsree999]

Great explanation bro

[@srikanthreddy7162]

nice explanation bro easy to understand

[@analoglayout]

Thx

[@youthcentral493]

Sir channel motivation is very super Sir

[@analoglayout]

kindly share my videos to your friends and college members , thx for your support

[@SubhashKumar9844066820]

Thanks for the video I was watching this video and got 1 doubt ;Antenna errors can be seen only on signal nets not on power rails ??

[@analoglayout]

Antenna will be on always gate connected net , gate signals will be anything , i.e signal , power , cock ,etc

[@samarthurankar8169]

Sir as you told to discharge the the charges we are using reverse biased condition diode. So that diode should undergo reverse breakdown and then it will start conducting so my question is what if we use forward biased condition diode directly so that the charges can discharge easily.

[@anuraggarg22]

Nice informative video. It would be much better if it is ads-free.

[@analoglayout]

Only from ads we are getting little revenue,go for youtube premium if you want ads free videos,that's the only option

[@surajgudigar8992]

Dude one more request we are waiting for twin tub concept

[@sai_ntr6574]

hi sir.your lectures are good and understandable. Also Make a video for electrostatic discharge sir.

[@analoglayout]

sure , il cover all the topic

[@rakeshlanderi8146]

Increase video quality from 480mp to 1080 mp , some words are not visible

[@analoglayout]

Don't use mobile phone, use laptop you can able to watch 1080

[@sultanabegumdotajoddinmous6302]

Sir please put for finfet cocepts like about finfet , double patterning , concepts of layouts in finfet

[@ramamurthy7937]

Do Physical design concepts soon sir, we are waiting

[@analoglayout]

sorry bro , in analog only i couldn't able to post full concept , bcos lack of time , PD concept will take time , bcos i need to prepare pd , give me some time

[@ramamurthy7937]

Analog Layout ok sir

[@analoglayout]

i will start pd also soon

[@ramamurthy7937]

Ok sit thank you , we will always support for Ur great work

[@sridevitalluri2367]

What are the benefits of using copper than aluminium for our metal layers???

[@youthcentral493]

Sir super Sir very like you sir Tamil video is very expensive

[@vaishnavinarkhede3900]

Can you please explain the functioning of circuit in the last slide? How is the load transistor acting as a diode? It still has 3 terminals- SG , D and bulk. And how the charges are getting dissipated at the time of manufacturing? What is the purpose of that load transistor? Please explain.

[@mrashokkumarkpm]

Hi sir.. thanks for the video.. it really helped me to understand the basics in a clear manner.. i need little more info regarding the usage of pass transistor to reduce antenna violation! thanks...

[@iclabs]

Nice video sir.

[@analoglayout]

Thx & welcome

[@xinyuanwang6400]

how does photolithography relate to charges building up in the metal? And why does the copper process not cause charge buildup?

[@analoglayout]

Photolithography is not a matter , I have clearly explain due to plasma is the charges are accumulated , and also copper fabrication is totally different way, it's a kind of trench formation technique they used to form copper

[@youthcentral493]

Sir briefly explain Integrated circuit in VLSI

[@mokkarallasivaramakrishna1645]

how the charge gets discharged by planarization?

[@analoglayout]

Read about planarization ......

[@venkateshnaidudulla3625]

Good work bro

[@user-ep4hz6nq5y]

During jumper insertion (Suppose M2 is used) Suppose if we got antenna error for long metal wire M1 then we want to use M2 in between . So the place where we want to fabricate M2 , at that place is M1 removed by etching ? Or again M1 and M2 are fabricated separately???

[@analoglayout]

Please read how metals are fabricated , u should not keep m1 , remove your m1 where your placing your m2

[@user-ep4hz6nq5y]

@@analoglayout thank you Sir

[@sharathseshadri3634]

First m1 will be fabricated and then m2 and so on

[@Saisoudha]

Nice explanation Sir

[@sudheshnamaroju7411]

sir y only gate is having the oxide layer ,can u please answer it

[@analoglayout]

I've explained in this video ... Pls watchit properly

[@sunnygupta6438]

Hi Sir, As you explain here during plasma etching positive charge accumulated to metal plates. So why positive charge ?Because plasma is hot ionized gas and always neutral (containing equal no. of positive and negative ions). please explain I am little bit confuse.

[@analoglayout]

Both the charges will accumulate , but nagative will not affect

[@saravanakumara8080]

Nice explanation. Need video on chip fabrication

[@analoglayout]

Already I upload , nwell process .... Pls take a look

[@rahultheytv5347]

Thank you so much sir fantastic

[@ashokreddygangasani5345]

hello sir why we do not go for m0 layer* ,we choosing higher metal.any reason to choose higher metal

[@dilipkumar-xg2ht]

Good explanation.When can we physical design videos?

[@sireeshakosanam5522]

I have a doubt on this.could u pls clarify that..how the gate oxide is dameged by accumulating charges on the metal.and this issues come in fab process..during fab processes they did not gave any power supply then how oxide is dameged pls clarify..

[@analoglayout]

Charge are formed by plasma etching , that's the concept of antenna

[@vishalmanchanda4213]

So for the fdsoi process , antenna effect will be seen for both drain and source??

[@sharathseshadri3698]

is the diode same for both pmos & nmos

[@analoglayout]

Ys, gate is always working as a capacitor regardless of nmos & pmos

[@vetrivelup3903]

Hi sir i have doubt regarding charges accumulation on metal why only positive charges ?

[@analoglayout]

Bcos plasma have only positive charge ion , thr is no nagative , wafer substrate is a nagative terminal

[@saisowmyamiriyala3074]

Sir!why we are using only higher metals for metal jumper

[@analoglayout]

Already we have a video for this , pls watch

[@amolboke2866]

I cannot find .clf file to check the antenna DRC . Please tell me where to find or how i can create that .clf file. I am working in Synopsis ICC

[@analoglayout]

There are some extra DRC ruel file to CHK antenna DRC

[@suryaramalingam2949]

Sir your saying it's a positive ions why can't it's may be a negative ions how ur saying it's only a positive how we know ? please could you clarify I have doubt on this from long time

[@analoglayout]

watch " what is plasma " in our channel , you will get the ans

[@RamaKrishna-cb3yd]

By connecting forward biase diode near by at gate what will happen

[@krishnavarma3075]

why shouldn't we connect antenna diode in forward bias? can u please explain sir

[@analoglayout]

Watch this ; kzbin.info/www/bejne/l6SUZWWgfMtohas

[@siddisrinuvaasulareddy1325]

What if both diode insertation and metal jumper not possible what will we do?

[@analoglayout]

Change complete routing or fp

[@mrashokkumarkpm]

Sir, u explained during Aluminium fabrication for lower metal layers, we do photolithography itching , and its a costlier one consuming 30% of manuf cost. so if some foundaries are using all the metal layers with Al (30:58) then how cost will be low ? since u told while fabricating copper in the 2nd method, no photolithography tech is used so, if its the case then cu fab cost is less than Al right sir.. Plz correct me if my understanding is wrong...

[@analoglayout]

Not all the foundry will do the same method ,it's depand on fab unit

[@mrashokkumarkpm]

@@analoglayout ok nanri thalaiva..

[@SubhashKumar9844066820]

why do we see Antenna violation on longer floating signals. how these floating metals impacts on design performance.?

[@analoglayout]

Already I've given more videos for antenna , try to watch all the antenna concept video's ...

[@SubhashKumar9844066820]

I have a clock signal where antenna violation is popping. i added reverse biased N- diode to clock . is this going to create any leakage in clock path?

[@analoglayout]

Ya ... Leakage Wil be there , but very low leakage

[@bindumadhavi3928]

how the charges will be accumulated on the metal plate while doing plasma etching??

[@analoglayout]

Charge are formed while plasma proces , those charges will attracted by metal

[@bindumadhavi3928]

@@analoglayout thanku you

[@krishnasoorannavar2063]

Dry etching uses intense electrical fields to generate an ionizing plasma.

[@bindumadhavi3928]

@@krishnasoorannavar2063 Intense electrical fields means?

[@shitalaher305]

Could you please make video on VLSI design flow?

[@nazianazneen8446]

Very nice explanation...for drawing are you using digital pen or any other software? please tell me..

[@analoglayout]

I'm using digital pen , with touchscreen laptop

[@nazianazneen8446]

@@analoglayout awesome

[@dasarinikhil14]

in interview i got a question like there's no scope to add diode & to use metal jumpers then how you will clean the Antenna. is it possible ,anyone help me with this

[@analoglayout]

Change the device Placement are or routing

[@pra590]

Any good online courses for layout design .

[@analoglayout]

We are offering online session, mail me for more info

[@youthcentral493]

And briefly explain physical design

[@analoglayout]

PD i will update ASAP with new videos

[@sharathseshadri3634]

VIA anntena explanation?

[@kurmachandrashekarkollati1756]

While fabrication we won't connect the ground terminal to gate then how charge will discharge from reverse bias diode

[@kurmachandrashekarkollati1756]

Sorry gd to diode***

[@analoglayout]

There no point of connection gate to ground , by default sub will be connected to gnd , on our gate terminal positive ions will accumulate ....

[@kurmachandrashekarkollati1756]

@@analoglayout Not gate terminal substrate only. how substrate connected to ground while fabrication can you explain bcz inorder to connect substrate also we need to fabricate M1 for tap then only we will connect. While this process gate may effect right.

[@kurmachandrashekarkollati1756]

I asked how gate connected to positive terminal of diode while fabrication.

[@sampathkumarmatlapudi8250]

if metal 2 has antenna violation, if we have possible to go to metal 1

[@analoglayout]

no , higher metal only advisory

[@sampathkumarmatlapudi8250]

why we are not goto metal 1

[@analoglayout]

bcos aft manufacturing metal 1 , will go metal 2 , the how again u will go for lower metal , its not possible

[@sampathkumarmatlapudi8250]

but we are checking antenna in layout on that casee

[@analoglayout]

if we cant make physically IC , y we need to design layout ?? if u have experience in real time , u can understood easily

[@kiranmai8773]

How insulator acta as a capacitance

[@user-ep4hz6nq5y]

Antenna ratio

[@analoglayout]

This value I took as a example & if you need any details regarding antenna , you can refer DRM manual

[@user-ep4hz6nq5y]

@@analoglayout ok sir

[@imhareesh9096]

What happen if I short gate, drain, source terminals..?

[@analoglayout]

it became dummy device

[@imhareesh9096]

@@analoglayout by using this is there any power related issues..?

[@analoglayout]

@@imhareesh9096 no , nthg will happ related to power

[@mohammedafzal534]

How more number of chargers will accumulate on metal & what are the layers present in n diode why can't we use p diode

[@analoglayout]

the reason for n diode placing i explained , remaining 2 question il upload new video

[@mohammedafzal534]

Ok sir

[@surajgudigar8992]

usually we use N type diode for simplicity when we are already using P+ as the substrate. If you are going to use pdiode then it will require additional biasing for its nwell.

[@analoglayout]

thx for the answer , i already posted a video reason for n diode separately , pls watch video

[@analoglayout]

thx for the answer , i already posted a video reason for n diode separately , pls watch video

[@pinkishrivas4882]

what is relation between antenna and antenna effect in vlsi design? how and when this effect came? and who's the observed this effect?

[@analoglayout]

Ru ? Fresher ? Or trying to learn ? VLSI . Seriously I'm not able to understand your mentality , I've clearly explained everything in this video , ABT antenna and antenna related stuffs , but still Ur asking basic questions , Better try to watch the complete video , if Ur not able understand watch it multiple times , may be used will get some ideas ABT this

[@pinkishrivas4882]

i am trying to learn Vlsi design.

[@pinkishrivas4882]

@@analoglayout i understood clearly .

[@TRUELiGHTERS]

stupidly lengthy video

[@analoglayout]

Pls don't waste your time ....