Design of a Dual Edge Flip Flop

[@RandomHubbb]

You are amazing! All of your videos are gold! Pure beef no fat. Thank you so much for your commitment to bettering us!

[@TechnicalBytes]

Thanks

[@Honest_Engineer]

Why can’t we use 1 flop and 1 MUX to implement this logic ? This will save area too. My solution is to drive clock bar itself on the select line of the MUX where 0 : Clk and 1: Clk bar , the output of the MUX then feeds to the D flop clock.

[@TechnicalBytes]

Actually, we don't want to place anything on the clock signal. Because clock travels on the clock tree, with lot of skew adjustments and other stuff is taken care. Adding user logic on the clock path is not recommended practice unless and until extremely required and approved by EDA tool flows. E. G. Clock gating and clock muxing.

[@DeepakKumarbidhuri]

great approach & best interview question ever

[@TechnicalBytes]

Thanks Deepak

[@shri1527]

pls also explain clock tree and sizing of mos required in clock tree in future videos .. I appreciate your work

[@TechnicalBytes]

sure Shrikant

[@arpittiwari7695]

I didn't understand why can't we use the signal which is used as clock to flip-flops as the signal at the select line of the mux?

[@TechnicalBytes]

@Arpit Inside ASIC and FPGAs clock travels on the clock tree so that we can ensure that its active edges are reaching to all the flops at the same time. Clock is very critical. So, If you start feeding this signal as a data signal to the combinational logic. Combinational logic can be anything depending upon our design. So, we will fail to ensure that clock is reaching to all the flip flops at the same time. Timing will definitely not met. Moreover, PNR tools will not allow this mapping. Let me know if you need any further clarification.

[@yamini7208]

Can you please elaborate this answer.....I didn't get this

[@prabhakarreddy9729]

One small doubt we can keep or gate instead of mux

[@TechnicalBytes]

No dear, suppose posedge flop sampled logic 1 .. OR gate will give its output as 1 irrespective of input from negedge flop .. now, on the next negedge suppose negedge flop samples logic 0. now, OR gate will still pass logic 1 because second input from posedge flop is logic 1 (posedge flop will hold logic 1 till next posedge). As per our expectation, on negative edge negedge flop data to be passed at output.

[@yamini7208]

Can you please elaborate ...why can't we use clock as Data signal....

[@TechnicalBytes]

@Yamini Clock travels to all the Flip Flops inside the design on the clock tree .. Most of the digital designs are synchronous digital designs. For synchronous digital designs to work, we need to ensure that clock to all the flip flops reaches at the same time or with some minimum delay, this is ensured by clock tree. if we start using clock signal as a data signal, data path can add any amount of delay. We will not have any control on the clock path. So, always avoid to use clock as a data signal. Hope it answered your question. Let me know if you have any further queries.

[@divyasirikonda8423]

Mux is a combinational logic device right, so we cant give clock signal directly to mux

[@AVINASHKUMAR-yd1gp]

To get the Clock like signal we used loops, Don't we avoid using loops to avoid glitches and Metastability

[@TechnicalBytes]

Dear Avinash, please go through this video.. perhaps it will give you answer of your question. Otherwise, let me know if you need more clarification. kzbin.info/www/bejne/pV66pGeOotitfKs

[@ranveerdhawan5187]

Superb

[@TechnicalBytes]

Thanks 🤗

[@divyasirikonda8423]

Can you provide video on designing MOD N Counter

[@rahulsriram7179]

Thank You ..

[@TechnicalBytes]

Most welcome !!

[@surajkole3472]

I am not able to join your KZbin subscription.

[@TechnicalBytes]

are you talking about membership? Many people are joining recently, they did not report this. BTW, what is the problem that you are facing???? I will take help from youtube team.

[@surajkole3472]

@@TechnicalBytes hi, when I try to pay the joining fee, my transaction is getting declined. I haved tried using adding balance in Google Play pay. It is showing option to pay from it. But when I try to pay it, it get's declined

[@TechnicalBytes]

Hello Suraj, please try to use other methods of payment like netbanking etc..

[@surajkole3472]

@@TechnicalBytes hi, I cannot see any other options apart from card and Google Play pay, both are failing for me.

[@TechnicalBytes]

Hello Suraj, Just now had a discussion with youtube team. they are asking to send them a short video clip of the error. Can you please share if possible?