What is Dual Edge Triggered Flip Flop? How to design it?🤔 Explained 👍

[@manojvippala184]

Good video thanks 🙏

[@KarthikVippala]

Namaskaram manoj🙏, thanks for the support, good luck & great health 👍😊

[@golinagasandesh4464]

Animations are really GREAT!!🤩

[@KarthikVippala]

Thank you 🙏

[@vaibhavjain5978]

Underrated channel

[@KarthikVippala]

Namaskaram 🙏 vaibhav , thanks for the support, good luck & great health 👍😊 take care.

[@luzengyuan5326]

this is nice to design bus-width change using double edge clock.

[@KarthikVippala]

Namaste lu zengyuan🙏 , thanks for the support, good luck & great health 👍😊

[@tomurkin5563]

This is a great video! Thanks :)

[@KarthikVippala]

Namaste Tom 🙏, thanks for the support, good luck and great health 👍😊

[@Placement_]

Hey Karthik we use dual edge flip flop to shift our signal by half clock cycle but in your waveform we are getting same output which we are giving so is it correct ? Please Reply ASAP.

[@KarthikVippala]

Waveform shown is for ideal case, actually there will be a delay due to flops.

[@Placement_]

@@KarthikVippala Okay Thank You

[@AbhinavAndFriends]

Is D becoming 1 just before the clock edge? Otherwise P wont become 1 right away. It will become 1 on the next posedge.

[@meghashree5535]

Thank you😊

[@KarthikVippala]

Namaskaram shree🙏, thanks for the support, good luck & great health 👍😊

[@rajyaganeshv8072]

Thank you ❤️

[@KarthikVippala]

Namaskaram 🙏,Wow !! Thanks for watching , good luck & great health 👍😊

[@gauthamsai7506]

On seeing this circuit something stuck me and I have tried giving two different inputs for the two flip flops and potentially can be used as a DDR unit

[@KarthikVippala]

Namaste 🙏,Gautham yes 😊 , you are correct , det is used as ddr, good luck & great health 👍😀

[@rbemra]

Wish you had used: (1) clock edges centered in middle of data D bits (2) D toggling in 1 clock cycle

[@bennguyen1313]

Aside from DDR applications, wouldn't another common application be SPI.. where you want to sample MOSI data on the rising edge, while updating MISO on the falling edge? reg p,n; always @(posedge clk) p

[@mounikabhuma8631]

Sir what is throughput and it's significance

[@KarthikVippala]

Namaste 🙏 Mounika, Throughput :The amount of data moved successfully from one place to another in a given time period . So more it is more better. Thanks for asking good luck and great health 👍😊

[@qingyuan3876]

2 xor delay, not high performance

[@vlogfreak4411]

what if we tale the case of p and D first rather than n and D ?... then answer will be reverse ...isn't?