FIFO Depth Calculation | How to Calculate FIFO Depth | Clock Domain crossing | CDC | VLSI Interview

[@Sachindeo93]

One small note here: Since you are designing asynchronous fifo, you need to take delay for synchronizes into the account (unless told not to assume by the interviewer/examiner). So it will be addition by 2 or 3 (depends on clock frequencies and how much stage synchronizers you are using for pointer crossing the domains) into the depth value, as you need empty to be de-asserted before the first read can start.

[@Electronicspedia]

Yes I agree with this. Thanks for bringing this point. 👍👍 I will pin your comments, so others can take a look.

[@abhijeetchauhan4111]

Suppose I use 2FF for CDC, how many clk cycles I have to add as extra delays ?

[@Electronicspedia]

@@abhijeetchauhan4111 Usually metastability settles in +/- 1 clock cycle on number of stages in synchronizers. This information you will get in synchronizers library datasheet.

[@abhijeetchauhan4111]

@@Electronicspedia So will it take one extra cycle for every read/write or one extra cycle for all read/write together. I mean whil creating fifo depth, do I need to add +1 in the final depth calculation or I need to take one extra cycle for each read/write ?

[@Electronicspedia]

Yes that's correct. We need to take extra depth. This because we have to synchronize read pointers to calculate full condition And synchronize write pointer to calculate empty condition

[@tarunkohli8047]

Please add more factors and cover all interview questions.

[@ginozhang0184]

Thank you so much for your sharing. It's very useful !

[@Electronicspedia]

Keep watching. Happy Learning 👍

[@Electronicspedia]

Please Like, Share and Subscribe to my channel kzbin.info

[@karthishanmugam5674]

Thanks for sharing sir,it is more useful sir I have some doubts in the fifo depth calculation sir 1,if write frequency is greater that read frequency and infinite data sir, that means no limit in data transfer and no idle cycle sir, that is the minimum depth calculation for fifo sir. 2,if write and read frequency are same only difference is phase is different sir and no idle cycle and transfer infinite data sir, what is the minimum depth calculation sir. Thanks for advance sir

[@Electronicspedia]

In case 1 , the FIFO will over flow if there is a infinite data transfer at some point of time. So we can not calculate FIFO depth in this case In case 2, ideally you need 1 deep FIFO. but since we have synchronizers in the design , we need to take those into account. Fifo depth = 1 + number of stages synchronizers

[@karthishanmugam5674]

@@Electronicspedia Thanks sir, for case 2 which module need to synchronious sir for write or read clock,both are same frequency only change is phases only sir

[@mbuaesenju8514]

Thank you.

[@ginozhang0184]

Could you please explain how ping pong memory design works ? I would appreciate it.

[@Electronicspedia]

Sure I have taken a note. Will explain in future videos. Thanks for suggesting.

[@IITMIAN_ABHILASH]

Dear sir why we need to substract 25 from 100 in the depth calculation 9:52.