LATCH UP PREVENTION

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Analog Layout & Design

Analog Layout & Design

Күн бұрын

Пікірлер
@nikkiscars4222
@nikkiscars4222 3 жыл бұрын
Another way of preventing latch up is P ring around P device and N ring around N device which will act as collector and reduces the BJT collector current and hence the beta
@analoglayoutdesign2342
@analoglayoutdesign2342 5 жыл бұрын
If anyone needs to discuss further, please send me a text on +91 7892400015
@arun65394
@arun65394 5 жыл бұрын
Hello sir, You taught very well, it is great insight to learn new prevention techniques... Thank you so much sir...
@mrashokkumarkpm
@mrashokkumarkpm 4 жыл бұрын
Very neat explanation sir... Please continue your good work.. waiting for more videos ! 💐
@mistakesimake2012
@mistakesimake2012 4 жыл бұрын
You Guys are amazing .. and doing awesome work
@rajatmaheshwari186
@rajatmaheshwari186 3 жыл бұрын
Please also make video on FINFET LATCHUP.
@vnnmichael
@vnnmichael 10 ай бұрын
if substrate Resistance is reduced , how is it lowering the chance of forward bias or V(be) ? Please explain
@shahidafridi90
@shahidafridi90 4 жыл бұрын
well explained Sir !!
@lokeshsutar3476
@lokeshsutar3476 4 жыл бұрын
Thnk u sr...it was very helpfull
@lokeshsutar3476
@lokeshsutar3476 4 жыл бұрын
It was very helpfull...thnk you sr. Can we have a lecture on short channel effects in a MOSFET..... please...
@analoglayoutdesign2342
@analoglayoutdesign2342 4 жыл бұрын
yes yes...its in plan...
@211SANDEEP211
@211SANDEEP211 5 жыл бұрын
Thanks
@rohanyadala9096
@rohanyadala9096 2 жыл бұрын
Super...
@analoglayoutdesign2342
@analoglayoutdesign2342 2 жыл бұрын
Thank you
@ayyappann6860
@ayyappann6860 4 жыл бұрын
Why big devices has more chances of latchup in drivers?
@ramkumarmariyappan2659
@ramkumarmariyappan2659 3 жыл бұрын
Big devices has more Id due to that latchup can occur
@rajasekharnallamekala4950
@rajasekharnallamekala4950 4 жыл бұрын
if p sub is not connected to gnd , what will happen and which pblms will rise ?
@analoglayoutdesign2342
@analoglayoutdesign2342 4 жыл бұрын
in that case, where should it be connected? We cant leave it floating. Psub should be connected to thle most negative voltage of the design... generally 0v. otherwise there would be substrate diode or body diode forward biasing condition..meaning i connect substrate to 1V and drain of the NMOS to 0.2V, substate to drain pn junction (substrate is P and drain is N) will get fw biased. Many unpredictable things will happen... hope this answers
@rajasekharnallamekala4950
@rajasekharnallamekala4950 4 жыл бұрын
@@analoglayoutdesign2342 Wil u upload video on Op-amp and LDO .
@analoglayoutdesign2342
@analoglayoutdesign2342 4 жыл бұрын
yes...but will take little time....
@rajasekharnallamekala4950
@rajasekharnallamekala4950 4 жыл бұрын
@@analoglayoutdesign2342 OK thanks for your response
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