Review of a PCB Layout: Do you do same mistakes? - For Beginners (Part 2 of 4)

[@WilliamWeatherholtz]

Robert, thank you for this series! It's hard for beginners like me to know what pitfalls are common.

[@mdchethan]

Hi RF, very helpful, this kind of information is not easily available anywhere in the web. Thank you so much for sharing switching power supply layout tips.

[@aliuzel4211]

Great video series Robert. Thanks a lot.

[@manouchehrmail]

Thank you, Robert, for putting time and sharing this.

[@RobertFeranec]

Thank YOU Manu :)

[@vsilte2]

Great video series! Thanks for sharing! :)

[@GuillermoMakestuff]

Awesome series! thank you

[@ab-zp1gs]

Great video thank you again!

[@sc0or]

I didn't get UGATE trace width. We are talking about megaohms of an input impedance of a mosfet transistor. For me there is no need to make the trace so wide for micro amperes signals. But the shortness is really important (cause of the impedance) as you've said

[@thenickdude]

The gates of beefy MOSFETs have substantial capacitance, and so substantial current is needed to turn them on or off quickly to keep them out of their lossy linear region. Thin traces have high inductance which opposes that.

[@K.D.Fischer_HEPHY]

If Robert goes "Waoh !" you know its serious.

[@mattemito10000]

4:09 why should you make the mosfet gate trace so big?

[@AmitsLife]

Robert, Thank you so much

[@ismailovali6368]

Thank you so much Robert, I like you very much :)

[@IPridek]

Thank so much , Master

[@RobertFeranec]

thank you gustavo

[@akankshaupadhayay2352]

Hello Robert ,is it fine if tracks are at 90 degree?

[@exscape]

Is it OK to place the components on different board sides, and also use so many vias connecting everything? I recently built my first (and second, on one board) DC/DC converter, and the datasheet was fairly strict on placing all components including the controller on one side, and to connect everything on one layer.

[@jp_engineer]

Hi there, Everything relies on your design. is it OK to place the components on different board sides? Yes, since it does not hurt any rule inherent to your design. and also use so many vias connecting everything? Yes, explanation same as above. (eg.: If you have to draw a great amount of current you better have proper track, vias and/or plane. Remember also that current heats the board and then temperature affects components properties. Does your components handle heating? So, take care everything must be thought and rethought. Forward and backward.) Could you tell us your controller?

[@exscape]

I used the LT3755-1 and LT3797, but read a ton of application notes and other tips to learn before I started the layout. By a quick look at the datasheet of those parts, it seems I picked those tips up elsewhere. It was mostly about avoiding parasitic inductances, e.g. in the AC current paths.

[@RobertFeranec]

If you are asking about Switching power supply placement, ideally you may want to have the high current components (inductors, transistors) and output capacitors on one side. I have done some designs, where there was no space so we had to use VIAs and place some components on other side - these boards were working ok, but always if I can, I try to do the placement based on datasheet or reference board.

[@jp_engineer]

Very nice, Robert... Also, I use to put those PCB rules of the datasheet in the schematic too. It helps. and you?

[@RobertFeranec]

I create net classes and specify diff pairs in schematic, but I do not normally add rules into schematic. If we contract PCB layout, I setup the rules in PCB file by myself (so it is not necessary to keep them in schematic).

[@jp_engineer]

Oh sorry, I meant I use to write text like this one ( it's written in Portuguese, the IC is the MP1584 ): SCH drive.google.com/open?id=1PolqMS2-hZsiXLmbjGjbVuGnoO9doLPK Correspondent PCB Layout: drive.google.com/file/d/17lmhPQ2HqnhP-zFpvn8BMd1ytEaosCzY/view?usp=sharing Btw, net classes - Once I had defined a group of capacitive sensors. That made easy doing PCB layout. diff pairs - Learnt and trained on the VOIPAC board, but I didn't have the opportunity for a real board.

[@RobertFeranec]

Ah, yes, I add important notes about layout into schematic.

[@MayureshVaidya]

How do we know which trace/ signal is noisy and which is not?

[@jojo150393]

Right angles on polygon isn't a problem ? I always cut of this angle but I don't know if it's a real problem. What do you think?

[@RobertFeranec]

That is a very good question. I have been thinking same, but I have never done any special investigation about this topic. Many reference designs use right angles in polygons and I personally have never seen any problems connected with right angle polygons, so I keep using them. But honestly, I do not know answer if non right angle polygons are better - I have never read anything about that.

[@johnsjunk9157]

right angles in shapes can cause concentration of the E-field which could cause a potential arc at high voltages. Some also think right angles in shapes a a factor in EMI but the jury is still out. Either way, Cadence Allegro can chamfer corners on shapes to a 45 or a curve for every shape in the design, or on a shape by shape basis, with a single click

[@asmi06]

Why using wide tracks for gate connections? There is almost no current flowing (except gate capacitance charge/discharge). Also TI recommends to void ground plane under switching nets to reduce ground bounce. BTW if you want I can give you the layout of my Artix/DDR3/USB3/HDMI board to review and beat up. I'm also just beginning to route these kind of things, so there are surely million things wrong with it. It's not very complicated (it's a 6 layer board) if you look past a ton of decoupling caps for FPGA, there are just a lot of tracks, but they all belong to only a handful of parallel buses. I would really appreciate any suggestions to improve layout as I'm just getting into such fairly advanced boards and I'm sure there are many things I still need to learn.

[@RobertFeranec]

Doing layout is a lot about theory (what would be ideal) vs reality (what can we really do) and compromises (if we can not do it as recommended, how to do it). Here are a few things about layout recommendations from datasheet of the chip used in the video. From datasheet www.intersil.com/content/dam/Intersil/documents/isl6/isl6236a.pdf : "Mount the controller IC adjacent to the synchronous rectifier MOSFETs close to the hottest spot, preferably on the back side in order to keep UGATE, GND, and the LGATE gate drive lines short and wide. The LGATE gate trace must be short and wide, measuring 50 mils to 100 mils wide if the MOSFET is 1” from the controller device." GND connection - that is complicated stuff e.g. this is recommendation from datasheet: "Isolate the power components on the top side from the sensitive analog components on the bottom side with a ground shield. Use a separate PGND plane under the OUT1 and OUT2 sides (called PGND1 and PGND2). Avoid the introduction of AC currents into the PGND1 and PGND2 ground planes. Run the power plane ground currents on the top side only, if possible. Use a star ground connection on the power plane to minimize the crosstalk between OUT1 and OUT2." However, in reality when these power supplies are used for example in motherboards, you may want to keep solid GND planes and keep the stackup which is good for high speed signals (that is what I usually see). Also, what is very helpful, is to check layout of their own evaluation board: www.intersil.com/content/dam/Intersil/documents/an12/an1272.pdf PS: If you like and if you do not mind me to share your design on youtube, you can send it to me. However, please, I can not promise, that I will make video about your design. (I answered this to other people too, let see if we can do more layout reviews)

[@asmi06]

@Robert Feranec Where can I find your email address? You also told me to contact you via email on EVBlog regarding Orcad course, but I couldn't find you address.

[@RobertFeranec]

asmi06, please send it to our official email address. I do not want to write email address here as I may then receive spam, but you can find it down on our FEDEVEL Academy page: www.fedevel.com/academy/

[@benjaminfacouchere2395]

Regarding "almost no current flowing" on the gate track. That's of course wrong, there's (ideally) a lot of current flowing to charge/discharge the gate (capacitance) quickly. But there's not a lot of charge being transferred in one charge/discharge cycle. For practical purposes you should lay out your track resistance so that a few amps can flow. Of course you can deliberately add resistance (narrower track) to create a low pass filter in combo with the gate capacitance. There's also the aspect of ringing to take into account.

[@RobertFeranec]

As you both pointed out charge/discharge currents, yes, if you check the ISL6236A datasheet, you can see info like "LGATE Gate-Driver Sink Current = 3.3A" or "UGATE Gate-Driver Sink/Source Current = 2A".

[@marcoscuriel7741]

I have two questions that no one could give me a clear answer to. In USB is it better to have diferencial routing or Matching the length of the routes? In Crystal is it necesary to match length of the tracks ?

[@UpcycleElectronics]

Marcos Curiel I don't think it's important. I can't say definitively as I'm just a simple hobbyist and learning myself. However, when I look at examples on production PCB's, I do not see any examples of designs that have traces with matched impedance, aka tracks with zig zag like routing on one trace to match the length of the other. Looking at the examples I have people generally try to keep these elements routed evenly but it doesn't appear to be critical. I think the only time a differential pair is important is when we're dealing with very high speeds or differential signals for analogue sensors and/or amplification. -Jake

[@strictnonconformist7369]

@@UpcycleElectronics if you’re only concerned with the 1.5 Mb/s USB it may not matter much. USB has much faster modes than that, so consider the operating speed of the fastest USB version it’ll be using or passing through as the guide.

[@콩나물-j6l]

sr.. plz add korea trenslate to video i student product development , instrument design for Rehabilitation device

[@MrAmar20]

I getting in sir

[@bahadrguven-cu7mb]

Can you add english subtitle please?

[@fpgaking3534]

12:48 hmm... W-OW