Temperature Inversion in VLSI | Cell Delay variation with Temperature

[@nanoelectronicsdemystified]

This can also be explained by carrier concentration (CC) along with mobility degradation. In semiconductors as temp increases first CC dominates and then mobility degradation. At higher technology nodes, as the supply voltage is already high, there will be sufficient carriers available without any more room for generation, so mobility degradation straight away starts dominating. Hence delay will increase with temp. (That's why only 125C corner for setup at higher nodes). At lower nodes, the supply voltage will be lower, so there will be fewer carriers available and with temp, CC will increase, and hence delay will decrease. But after a certain point, mobility degradation starts dominating and again delay will increase will temp. So there will be U or V shape kind of graph for cell delay where extreme points having min and max temp with max delay. (That's why -40C and 125C both corners for setup at lower nodes)

[@reshmasaleem925]

Explained very well

[@TeamVLSI]

Yes, that's right.

[@awantikaupadhyay2891]

Nicely explained 😊 keep posting more interview related stuff Thanks

[@TeamVLSI]

Sure awantika👍 You can visit our blog more on interview guidance. www.teamvlsi.com/search/label/Interview%20Section

[@IC_design_Bellamkonda]

Excellent flow to understand the concept. There are many resources with concepts in statements but you have given nicely explained from equations to concepts towards statements. Great work bro. ❤

[@chandrakanth.m.s.63]

Felt Good. Impressed with the questions you asked in the video. Keeep posting new videos Sir.

[@TeamVLSI]

Thanks a lot Chandrakanth. Sure we will do that. keep supporting.

[@carthyck]

Thank you Sir. I got clarified in many doubts i.e., relation between temperature, power and delay.

[@TeamVLSI]

You are welcome Carthikeyan. Keep learning and keep giving feedbacks.

[@pavankumarVilasagar]

1. I think there is no change in Net delays from higher to lower tech nodes.. Because it purely depends on mobility of electrons.. So resistance increases with temperature 2. Hold will be checked at Minimum temperature at lower tech nodes because supply voltage is maximum so mobility plays a major role compared to Vgs-Vt

[@TeamVLSI]

Right Pavan.

[@pavankumarVilasagar]

@Alexandru Ionut EneGenerally the design performance will be checked at different voltages.. Vmax-Vtyp-Vmin.. For e.g. Lower technology nodes.. Vmax is 1.25v, Vtyp is 0. 9v, Vmin is 0.65v: For Higher tech nodes.. Vmax is 1.5v, Vtyp is 1.375v, Vmin is 1.25v.. So here the Vmin at higher tech nodes has become Vmax at lower tech nodes.. Hold will be checked at maximum voltage.. So when the voltage is more, less change in Vgs-Vt.. So the delay is less dependent on threshold voltage and more dependent on Mobility and mobility is inversely proportional to delay. At higher temperature Mobility will be less.. i. e. Delay is more. So device will be faster at lower temperature.

[@adarshchaturevdi4660]

Thank you so much, your way to explain is very good. 👍

[@TeamVLSI]

You are welcome!

[@nitiningle1991]

Very Nice and detailed explanation. Keep on doing good work. Your channel will definitely grow. 👍

[@TeamVLSI]

Thanks Nitin.

[@NandaKishore-zo8mw]

Thanks for your nice explanation !!!!

[@TeamVLSI]

You are most welcome Nanda.

[@parthsoparia6379]

HVT cells are more prone to temperature inversion as compared to SVT and LVT because, in hvt cells threshold voltage increase and thus overdrive voltage reduced (vdd-vt) which makes vdd and vt more comparable..

[@TeamVLSI]

Well explained Parth!

[@MrArunraja08]

Great example. Thanks

[@TeamVLSI]

Thanks a lot Arun!

[@soorajjp1847]

First comment Voice quality is greatly improved Short-Important Topic videos will be really helpful for Interview

[@TeamVLSI]

Thanks for your appreciation Sooraj!!

[@IC_design_Bellamkonda]

Is there any standard to differentiate the lower and higher technology nodes. Like 65n you mentioned.

[@sudhirkambhampati9027]

Hi , Thanks for the video . I have a suggestion .. You can take an example values for mobility , Vgs and vt and explain the variations.. Understood that the squared dominance of overdrive voltage in the lower technology nodes , but what about the mobility? Even that decreases right? So i think it is important to explain with a simple example how the mobility decrease is still not mattering much and how overdrive voltage is compensating that.. Lets look at this example : First of all i would like to simplify the id equation id = mobility * ( Vgs- Vt) square [ remaining everything is constant value ] Now lets take some real time values : at 180 nm , T = 0 degrees , mobility (m) = 100 , Vgs = 3 V , Vt = 0.6 V , id = 100 * 2.4V * 2.4V = 576 mA at 180 nm , T = 100 degrees , mobility (m) = 10 (because of lattice scattering , m reduced at high temp) , Vgs = 3 V , Vt = 0.4 V , id = 10 * 2.6V * 2.6V = 67.6 mA at 7 nm , T = 0 degrees , mobility (m) = 100 , Vgs = 0.7 V , Vt = 0.3 V , id = 100 * 0.4V * 0.4V = 16 mA at 7 nm , T = 100 degrees , mobility (m) = 10 (because of lattice scattering , m reduced at high temp , this is applicable even at lower nodes) , Vgs = 0.7 V , Vt = 0.35 V , id = 10 * 0.35 * 0.35 = 1.225mA Now to summarize as temperature increases from 0 --> 100 degrees , at 180 nm , the current reduced from 576 ma --> 67 mA but at 7 nm , if we assume same reduction in mobility , current is still reducing with increased temperature , 16 mA --> 1.225 mA , which doesn't still explain temperature inversion. Now the question is , will the mobility reduces with temperature in lower nodes? If yes , then how do we explain the increase in current with increased temperature with the above example.. Thanks

[@TeamVLSI]

Very nice explanation dear. Keep it up!!! Your points have been noted and will try to explain with numerical values in next time.

[@sudhirkambhampati9027]

@@TeamVLSI Can you please quickly clarify my question? "Now the question is , will the mobility reduces with temperature in lower nodes? If yes , then how do we explain the increase in current with increased temperature with the above example.. "

[@TeamVLSI]

Hi @Sudhir: Happy to read the analysis you tried. I would like to say three things in this regards: 1. Yes, Mobility decreases in temp range (300K to 400K) irrespective of technology node. 2. Decreasing Vt is not followed in the 7nm calculation of your example. 3. You need to calculate with the realistic data, ( 90% decrease is mobility in 100K temp change is not realistic) Currently I don't have, access of data, but you can take the following data and try to analyze. You will find the result which validate the whole concepts. 1. Take mobility 1400 and 1200 at T = 300K and 400K 2. For 180nm take VDD = 1.8V and ( Vt = 0.6V (T = 300K) and 0.55V ( T = 400K) 3. For 28nm take VDD = .7Vand ( Vt = 0.4V (T = 300K and 0.35V 9 T = 400K) Note: Above data is again not real but more realistic than previous.

[@TeamVLSI]

Since purpose of this video was just to make the topic clear, how to answer in interview, So detail analysis with result would make the video lengthy and mostly people dont like to go in details. :) Hope you understand.

[@TeamVLSI]

I don't know you are connected to our WhatsApp/telegram group or not? If not I would like to see you there. search "team VLSI " in telegram and connect and ping me there.

[@happysharma5635]

This is really very helpful. Keep making videos

[@TeamVLSI]

Glad it was helpful!

[@mekalagowthami162]

Hii sir..... At lower nodes we are getting temperature inversion, so what are the prevention techniques for temperature inversion at lower nodes. ..?

[@sudhirkambhampati9027]

Very good questions : Q. What is net delay variation with temperature .. does the net delay increase or decrease with temperature? Ans : To understand this , we know that a metal is a combination of R and C elements. So , all we need to know is what happens to R and C as a function of Temperature Lets start with R: R = R ref ( 1 + K ( T - Tref ) ) Where K is temperature coefficient of Resistance .. Now the most common metal used in fabrication is aluminium(180 nm) and copper ( < 28 nm ) and K is a positive number Which means , R at 100 degrees is a higher number than R at 0 degrees. Which means R value increases with Temperature -- ( 1 ) Lets analyse C : Capacitance variation with temperature is not straightforward like resistance. doesn't Now depending on what dielectric is used , C will increase or decrease with temperature . Assuming we are using aluminium electrolytic capacitor , cap increases by 8% with temperature. Now assuming both R and C increase with temperature , i believe with temperature , RC value should increase. Assuming same materials used for fabrication in 7 nm and 180 nm ( which is very unlikely ) , C value will increase with temperature. -- (2) From (1) and (2) RC value will increase with temperature. Q. Among HVT , SVT and ULVT , which cells will have maximum delay variation with temperature ? Ans : HVT cells has maximum delay variation with temperature HVT cell delay reduces by about 16% when temperature is varied from m40 to 110 where as LVT cell delay reduced by about 9% when temperature is varied from m40 to 110. This difference in delay % between HVT and LVT can be attributed to one single reason: in (vgs- vt) square , when we sweep the temperature from m40 to 110 , the rate at which the vt reduces for hvt is much higher than the rate at which it reduces for lvt. Please correct me if i am wrong. A question. Can we know what is the vt value from .lib?

[@TeamVLSI]

Wonderful Sudhir. Well explained!!

[@TeamVLSI]

Vt value in .lib? I need to check.

[@palakagarwal7156]

Very helpful

[@TeamVLSI]

Thanks Palak 😊

[@shreyanshsoni6148]

if delay is decreasing as the temperature is increasing and the circuit is becoming faster then it will generate more heat, so temperature will increase further which will form a positive loop and can damage the circuit.... am i right

[@vaibhavgera6486]

Hi, Can you explain lattice scattering?

[@TeamVLSI]

Ok, I will try.

[@soorajjp1847]

Kindly provide answers to questions asked in video description so that we can follow up

[@TeamVLSI]

Sure Sooraj, But let answer this question viewer first.

[@mshivu008]

I feel process graph what you showed for Lower nodes is not correct. In lower nodes also delay will increase with temperature. But not as much as in lower temperature. Graph Will look like elaborated 'U' shape.

[@TeamVLSI]

Hi Shiv, 1. I told in the video the graphs are only indicative to elaborate the trend only. 2. As I told in the video, at the lower node delay will decrease with temp due to the dominance of vt over mobility variation. Thank you.

[@TeamVLSI]

In case if you have any supporting documents of your statement, Please share, I would love to read that. Happy learning!

[@janicesweedal4877]

Temp is low for hold in worst case