how to adjust setup and hold time of a flip flop ??

[@meenugarg1102]

I was looking for this concept, thanks for sharing

[@TechnicalBytes]

Welcome

[@akshaysubash3176]

Sir if we give delay to the data path or clock path the corresponding signals will shift towards right. But here it shifted left, why?

[@TechnicalBytes]

you are right, when we add delay signals get shifted towards right. Samething is shown in the timing waveforms as well, let me explain Case1: Addition of delay on the data path. Data will be delayed to reach input D of a flip flop. D is right shifted w.r.t Data input. Is it right? Case 2: addition of delay on the clock path. Clk will be delayed to reach input C of a flip flop. C is right shofted w.r.t clk input. Is it right? Is it clear? or you need any further help?

[@rajmoulijujjavarapu3677]

I think if you want to increase your set up time, you need to have lower logic delay. Which means decrease the critical path. Isn’t that correct, I don’t see how adding delay to the data path increases set up time. Could you Elaborate.

[@TechnicalBytes]

if you want to consider FF to FF path. one of the flip flop through the data and other one captures it. Our diagrams are w.r.t capture flop. As you said, if we lower the logic delay, it will decrease the critical path delay. you are right here. Equation of a Tmin = Tcq + Tcl + Tsu if we add one extra delay at the flip flop input. Now, Tmin = Tcq+Tcl+Tcl_new+Tsu Or in other words, Tmin = Tcq+Tcl+Tsu_new Tsu_new = Tcl_new+Tsu Does it make sense now? Let me know if you have any query.

[@shri1527]

tnx sir for making such videos...its very helpful for vlsi/semiconductor field interviews.

[@TechnicalBytes]

Thanks for your complimentary comments

[@hemasid]

Very nicely explained. Thanks for sharing

[@TechnicalBytes]

My pleasure

[@ShwethaSubramanyam]

I understand setup time of a flop depends on the data transition and clock transition... But adding delay how the transition is increasing ? Can anyone please explain

[@TechnicalBytes]

What do you mean by data transition and clock transition? Can you please explain setup and hold time of a flip flop?

[@TechnicalBytes]

Actually, we can not change the setup and hold time of a flip flop. It is fixed. Let us name flip flop inputs as D and C. But if I put a delay on clock and data paths and form a new logic having inputs Data and Clk. Does it remain same flip flop only?? ANswer is NO. But this new logic is also working as a flip flop only, with changed setup and hold time. That is what I tried to explain in the lecture. Let me know if you have any concerns.

[@Athram8]

Adding SKEW or any logic to clock is correct ?? As many interviewers say it wrong to disturb the clock. Please explain !!

[@TechnicalBytes]

you are correct .. delays that we are talking about , are the delays of clock buffers on the clock tree ..

[@sumukhabharadwajmohanrao853]

That's a good point to raise. Even I was wondering about this! And these clock buffers are added by the tool itself. We don't have to add it manually.. Correct me if I am wrong!!

[@TechnicalBytes]

@@sumukhabharadwajmohanrao853 Depending upon the timing constraints given it adjusted the clock path delay and data path delay. it is controlled by the tool. But we can also intervene.

[@placementdas3997]

Can you please suggest a book for sta ?

[@vlogfreak4411]

but sir hold time does not depends on freq so how we can increase or decrese it by varying clock delay and data delay?

[@TechnicalBytes]

Actually, we can not change the setup and hold time of a flip flop. It is fixed. Let us name flip flop inputs as D and C. But if I put a delay on clock and data paths and form a new logic having inputs Data and Clk. Does it remain same flip flop only?? ANswer is NO. But this new logic is also working as a flip flop only, with changed setup and hold time. That is what I tried to explain in the lecture. Let me know if you have any concerns.

[@AVINASHKUMAR-yd1gp]

So, It's like the uncertainty principle we decrease setup time we get more hold. And Tsetup + Thold remain constant for a Flip flop no matter what logic we use. Please Correct if I am wrong

[@TechnicalBytes]

you are right.

[@pavankumarVilasagar]

Generally For setup, Required time = clock period + latency - Tsu_ff. So I understood that you are adjusting latency value not Tsu_ff.. Right?

[@TechnicalBytes]

Hi Pavan, I did not get what you are trying to say. Can you please eleborate??

[@pavankumarVilasagar]

@@TechnicalBytes I mean to say.. You are not changing the setup time of the flop.. You are adjusting the capture flop clock path delay

[@TechnicalBytes]

@@pavankumarVilasagar You are correct..

[@swapnilbande2067]

how it is possible if we increasing the delay on datapath will fix the setup violation? Decreasing the logic delay: Another way to reduce logic delay apart from replacing SVT and HVT cells with LVT is to change the logic in register transfer level (RTL). This will most of the time result in increased latency, resources, and power consumption but will ease timing requirement and solves setup time violation.

[@TechnicalBytes]

Hi Swapnil, no where I said that increasing datapath delay will fix setup violations. If you increase the datapath delay, it will increase the setup time and eventually, setup violation will go worst.