Verilog VHDL Interview Questions Part 1

[@meenugarg1102]

Amazing explanation, please share more videos... we are waiting

[@TechnicalBytes]

Sure Mam !!!!!!

[@NitishKumar-xw9qt]

At 4:22 the output Y should be of one bit because unary and is a reductional operator.so given problem can be thought of 8 input and gate .

[@TatharNuar]

4:06 I don't think Y is necessarily 8 bits here, unless you're assigning to an 8-bit bus. You could assign it to a 1-bit wire instead and it'd work as expected. Edit: I should have read the comments before repeating what everyone else said, oops.

[@carlosmaffrand2811]

I found a little mistake there is an unary operator en VHDL, and_reduce, or_reduce... and so on. you have to use std_logic_misc in VHDL 2003, and you can use out

[@gauravsingh3273]

for logical AND operator and unary AND operator output should only be 1 bit

[@TechnicalBytes]

you are right, but in verilog if you assign that 1 bit value to any variable with more number of bits.. then, it appears at the LSB bit.

[@SunitaRani-ww9oc]

Very nice!!

[@TechnicalBytes]

Thank you! Cheers!

[@ratansingh3086]

Superb Sir !!!!!

[@TechnicalBytes]

Keep Supporting !!!!!

[@manveersinghmehra]

good

[@TechnicalBytes]

Thanks

[@rahulsriram7179]

GOOD ..

[@TechnicalBytes]

Thank you !!

[@rakeshkrkeshari8122]

2nd part, please

[@TechnicalBytes]

Dear, when any video will end, you will get an end screen video .. please follow that .. kzbin.info/www/bejne/nXOZg2auaq1na5o