DVD - Lecture 2: Verilog

[@AdiTeman]

Note that there is a typo on Slide 16 (42:00). A latch should have the "d" input in the sensitivity list, so for a correct latch it should be: always@(d or en) or just always@* Thanks to Nour Daghlas for noticing this.

[@nguyenduykhoi7819]

Your explanation is clear and this course is created. Thank you very much!

[@AdiTeman]

Glad it was helpful!

[@suprajithhs5609]

This is a wonderful channel. This video is such a great resource to learn and relearn some of the tricky bits of Verilog. Regarding reg vs wire, I love what they did with SystemVerilog: everything is a "logic"! Thank you for the videos.

[@AdiTeman]

Thanks for the kind words. Indeed, System Verilog improves on many of the things that Verilog was not so good at. That being said, unfortunately, some tools still have trouble with various System Verilog constructs (especially interfaces) and this can give us chip designers quite a headache at different parts of the flow - sometimes even making us regret our decision to use the advanced features... In any case, I decided to teach Verilog in this course as it is still more universal, it is used in the structural (gate-level) output, and in general, it's not "all that" different. Glad you enjoyed.

[@little_explorers2866]

@@AdiTeman plz do video about system verilog

[@AdiTeman]

Maybe will do so some day. Thanks for the suggestion.

[@misuh9097]

Great comprehensive lectures. Thank you very much! One minor remark on slide 23, the else next_state CNTDN, perhaps count=='b0 should be used in the if statement instead of count==4'b0000 for the code to work with different counter widths.

[@AdiTeman]

Good point! Thanks.

[@hossamfadeel]

I really appreciate your efforts. Very Clear and Constructive. Keep Going. Thumps Up.

[@AdiTeman]

Thank you, I will

[@ramakishan7323]

Thank you Mr. Teeman for amazing lecture

[@AdiTeman]

You are very welcome

[@digvijaysingh4738]

Professor, the explanation in the videos is amazing. I am taking a PD and ESL course in university and the lectures help a lot. It would be really helpful for everyone if you could get your other digital design course lectures translated in English.

[@AdiTeman]

Thanks for the kind words. I would love to record the other courses in English, but I unfortunately don't have the time to do it right now. I hope that I will be able to do this in the future.

[@ibrahimmohamed1839]

Thanks Dr. Adam Teman for this useful lecture

[@AdiTeman]

You're welcome :)

[@AhmedAshraf-hg7gy]

I really loved your style of explanation, how great this lecture !! keep it on

[@AdiTeman]

Thank you!

[@chepurivenkatesh8238]

Thanks you very much professor. These lectures helped me a lot in my interviews

[@AdiTeman]

You are very welcome

[@ashwinsingh1325]

Hi professor, I was wondering why you needed to define overflow condition at 58:51 using: if(count==(1

[@AdiTeman]

Yes, indeed, this is to make the code parametric. For the zero vector, most simulators and synthesizers will pad with zeros, so we didn't need to write anything "fancy', but for the ones, this is a little trick to create a parametric ones vector.

[@chadwinters4285]

@@AdiTeman Hello. I'm coming from the VHDL world where there is the syntax like count=(count'range=>'1') to accomplish what you did to check for the '1111' condition. Out of curiosity, why didn't you use something like {COUNTER_WIDTH-1{1'b1}} to get the '1111' which is still parametric ?

[@AdiTeman]

Sorry for the late reply. Your question got away from me :) I think this could have been done as well. Just a habit of writing RTL in one way or another (tricks you pick up along the way). Any of these shorthands that work are fine.

[@yunzhongwang1655]

Hello, Professor, thanks for your great lectures, at around (38:00), why a latch will be inferred without an "else " statement? This question bothers me a lot, could you please give me some help? Thanks！

[@AdiTeman]

Hi Yunzhong, Let me try to explain. Combinatorial logic does not know how to "remember" things - for that you need a register (flip flop or latch). An assign statement is entered when anything in the sensitivity list (RHS) changes and has to decide what the new state of anything on the LHS is. If you have a clear answer to that for every possibility, then all is well. But if you don't have a clear answer, you have to "keep" whatever was there before, requiring "memory" or in other words - a latch. To try and better illustrate this, I will use the example of the lecture. The sensitivity list includes "sel" - so anytime "sel" changes, the always block will be initiated. Inside the always block we have "out" on the LHS. Therefore, the always block must "decide" what to drive onto "out" for every reason the always block was entered. The first statement "if (sel)" means that if sel=1 (e.g., sel toggled from 0 to 1), it will drive "a" onto "out". But what happens if sel==0? Well, the "else" takes care of that, but what if there was no "else"? The always block still has to decide what to drive onto "out". Should it drive "a"? No, that's only when sel==1. Should it drive "b"? No, why should it? The answer is, it should drive whatever it was driving before. How? By remembering what it was driving before. How could this be synthesized? Add a latch to the output of "out". The enable of the latch would be "sel". If sel==1 then the preceding logic (the mux) is propagated. If sel==0, the latch is closed and therefore whatever was there before is kept on the output. Hope that clarifies this point.

[@yunzhongwang1655]

@@AdiTeman Thanks a lot for your kind explanation, and I have understood it.😄

[@nourdaghlas9397]

Hi! First of all thank you for all the effort you put in the lectures and slides. They're amazing. I have a question -- At 42:00 you mentioned that the Verilog in that section is a latch, but suppose 'en' goes positive and 'd' gets passed to 'q', if 'd' changes while 'en' is positive, will that trigger assigning 'q' again or would you have to add 'd' into the sensitivity list for it to actually behave as a latch? Or is it understood that as long as 'en' is positive, 'q

[@AdiTeman]

You are 100% correct. This is a bug in the slide. For a true latch, the enable and the data should be in the sensitivity list. So if you were to write the code as in the slide, this would require some additional logic from the synthesizer. I will try to fix it at some point (unfortunately, the built in editing tools in KZbin don't allow this type of editing, so I need to rerender and upload it...). Thanks again for the comment!

[@nourdaghlas9397]

​@@AdiTeman Thank you for confirming. I'm not much of a verilog person so I'm sorry I couldn't test it myself. If I may suggest, adding whatever corrections for a video in a pinned comment would be a good place for all to see since I'd wager most people at least do get a look at the first(pinned) comment as they're usually reserved for important info regarding the video. Otherwise all the effort in upkeeping the lessons is of course much appreciated! :)

[@AdiTeman]

Thanks again. I wasn't aware of this capability. I have added a comment and pinned it (at least until I have a chance to fix and upload a new video)

[@СеменМоскаленко-ь7и]

Really good lectures, thanks from Russia

[@AdiTeman]

Your welcome. It's my pleasure!

[@iliachakarov7285]

Now this lecture I like!! gj

[@AdiTeman]

Glad to hear that!

[@AmeenAltajer]

Great series, thank you so much.

[@AdiTeman]

You're very welcome!

[@swastikkhuntia3283]

Great lectures sir🙇‍♂️🙇‍♂️Much obliged for your effort. Have been constantly following your lectures. One thing that struck my mind at around 59:00 , that instead of doing the shift operation and -1 for detecting overflow, couldn't we have used a reduction & operator, and reduction ~& for overflow during down counting? I think it would have been a bit simpler. Your lessions are great sir😁😁

[@AdiTeman]

Yes, something like that could for sure be done. In fact, there are many tricks that veteran designers play to "fancify" their code. I just wanted to show one such example. That being said, note that when using these alternative ways to write something: 1) You need to carefully verify it to make sure you weren't too sophisticated for yourself... 2) You should think about the synthesis implications of your coding style. I go over some examples of this in the next lectures. Some coding styles could lead to more complex hardware or hardware that is not 100% equivalent, so make sure to think about this when using such tricks. 3) Sometimes writing "fancy" code makes it harder to read and therefore, harder to maintain and debug. If you do these tricks, make sure to comment/document them clearly or you will be sorry when you return to this line of code later on.

[@cmeditz9988]

Sir can u make a vedio on how to use spyglass and design compiler for lintingand synthesis

[@AdiTeman]

I will indeed add it to my wish list of videos to make.

[@ykrishnateja8871]

Hello Professor, In the expression count==(1

[@hongle-pr7mo]

Hi professor, thank you for a very throughout lecture. I was wondering if is there any ways that I could get the powerpoint of the lectures. The attached link in the description does not work.

[@AdiTeman]

Hi Hong Le, Indeed, the faculty website is down due to security concerns. If you need to access the slides in the meantime, please email me at [e-mail] and tell me which slide decks you need. I also may move them to a different server if it is not resolved soon. Thank for your interest, Adi

[@AdiTeman]

My faculty website is back online www.eng.biu.ac.il/temanad/teaching/

[@HsinYuChang_chy1982]

Thank you so much. It helps me a lot.

[@AdiTeman]

Glad to hear that!

[@TNTsundar]

Great lecture! I wonder if this covers almost all the aspects of Verilog. In other words, the language seems to be using a small set of keywords and constructs unlink C like programming language where there are much more detailed construct and ideas that are frequently employed in drivers, firmware and applications.

[@AdiTeman]

Hi Sundar, In no way does this lecture cover all that is available in Verilog. There are pretty thick books for that. But I tried to narrow it down to the 80% (maybe more) that is most often used for RTL coding and basic testbenching. If you can conceive this very limited content, you can pretty much start coding. The nooks and crannies to do more tricky stuff are easily searchable on the web or in a text book, but I don't think they're at all necessary when starting and the more syntax, the more confusing things get. So I decided to skip all of that for an introductory lecture, and let stack overflow provide you with the rest :)

[@TNTsundar]

@@AdiTeman Thank you for the response. Your lecture is very easy to understand and provides a good introduction to HDL. Please keep it going.

[@gauravdewangan2765]

Thank you so much sir.

[@AdiTeman]

Most welcome

[@amitr24]

Thanks!