latchup

[@chiraag3972]

Pretty challenging to find the exact explanation of latch-up problems. This video is amazing and explains exactly what you need to know about latch-up with BJT basics. Thanks a lot!

[@gundloo]

Great job of explaining an involved concept of latch-up.

[@sunnygupta6438]

Thanks to you sir 👍 they way of explaining of the topic is great .

[@gonchar80]

It's awesome explanation, the BEST i've had hear

[@mounikayadav9685]

Sir please explain about finfet... Your explanation is very well....

[@arun65394]

Thanks a lot sir. It is really helpful to understand the impact of Beta value.

[@analoglayoutdesign2342]

Should you have other questions, please post it in the comments section..thanks

[@arun65394]

Hello sir, Can you pls explain about how guard ring will reduce resistance and how can we say that all are in parallel connection?

[@analoglayoutdesign2342]

@@arun65394 ...sure..I will upload one more video to explain prevention of latch up..I will explain in detail..

[@arun65394]

@@analoglayoutdesign2342 Thanks a lot sir...

[@analoglayoutdesign2342]

I have uploaded a video on latchup prevention. Please go thru. Let me know if further details are required.

[@eswareswar1538]

It's awesome explanation sir , Thanks alot .

[@analoglayoutdesign2342]

Thanks for the feedback

[@nikkiscars4222]

Latch up occurs on pad connected devices due to ESD . Please add this point too

[@randomsstudioo]

great explanation

[@analoglayoutdesign2342]

Thanks for the feedback

[@ramadevikothapalli8743]

Nice explanation sir Pls do more vedios on several topics of layout and lower nodes sir

[@analoglayoutdesign2342]

Sure..will.do..thanks for feedback

[@chandanasudunagunta8230]

Sir very understandable explanation, y only latch up occurs in final stage of drivers only, please clarify. Thank you

[@analoglayoutdesign2342]

Hi.. it’s explained in the video only.. where you have big transistors NMOS and pmos, the parasitic npn and pnp transistors form.. otherwise, for every small inverter, there would be latch up and cmos process could not be used at all..

[@vimakuma]

Whenever I get rejected in any interview and can't explain how the latch up works. I just come here and revise my basic 😭😭😭

[@analoglayoutdesign2342]

Always be prepared.. if you understand the concept, no need to prepare again and again

[@SM-ob5sm]

best explanation

[@analoglayoutdesign2342]

Thanks for the feedback

[@varunde95]

sir make videos on all failure mechanisms including wpe sti lod antenna em and ir and thank you for this video.

[@analoglayoutdesign2342]

Hi Varun, I have now uploaded WPE video. Please go thru. hopefully its informative.

[@varunde95]

@@analoglayoutdesign2342 tysm sir

[@vnnmichael]

Sir how reducing the Resistance is preventing the forward bias of the BJT Transistors ?

[@analoglayoutdesign2342]

Vbe is voltage across base emitter.. we have resistance in parallel to it.. that is, if a current flows thru the resistor, it will create a voltage drop across it, which is nothing but voltage, vbe.. if resistance is less, then voltage drop is less or vbe is less and base emitter junction is not forward biased.. hope this answers

[@anilsn8219]

Hi Sir, if there is a power bounce there is a good chance that it will affect other circuits also, how do we take care of this?

[@analoglayoutdesign2342]

if its digital ckt, noise margins will anyway be there...but if analog ckts are connected, we need to take care...please watch Agnd,DGnd & isolation video

[@digambarbhole9467]

sir , @ 14:14 how the substrate taps(i.e gaurd ring) is reducing R1 and R2 can you please explain??

[@analoglayoutdesign2342]

Hi, please listen to the video again.. bcos when you put substrate taps, the resistance to the bulk connection reduces

[@meghachandargi6805]

Thank u sir

[@rakeshyerragopu1298]

AT 7:41 in Feedback LOOP one direction of current is wrong, I guess Ic of PNP should be upwards

[@leviwow7741]

No, it's not wrong.

[@kshitij8810]

Sir can you please explain how do well tap cells prevent latchup?

[@analoglayoutdesign2342]

Please watch another video "latchup prevention" everything is clearly explained

[@SudhirSingh-yb2de]

sir, how will be initial base to emitter voltage of npn transistor is greater than 0.7v

[@analoglayoutdesign2342]

Didn't get your question. Can you please reframe and elaborate it.

[@rakeshyerragopu1298]

Suppose, noise

[@microsoftmath]

I THINK 0.7 v is when the impurity is germanium

[@ranjitneelakandan9551]

One question, the 1.8 and 3.3 V that are used do they come from a bandgap source ?

[@analoglayoutdesign2342]

Are you referring to level shifters? If yes, then 1.8v is core supply and 3.3v is I/O supply. Bandgap references cant drive level shifters

[@ranjitneelakandan9551]

@@analoglayoutdesign2342 So as I understand Band gap is used for accurate voltage reference like in ADC etc.

[@ranjitneelakandan9551]

@@analoglayoutdesign2342 Thank you for your reply.My background is more in signal processing algorithm design but taken a keen interest in Analog design.Do you have any plans to use open source tools like skywater pdk along with layout tool like Magic.It would interesting to design the concepts discussed like current mirrors,etc. Thank you again, I learnt a lot from this.

[@analoglayoutdesign2342]

True..that's correct

[@analoglayoutdesign2342]

Ok..got your background. Yes I have done that in the past. But I generally give introduction to topics here in this channel.. Don't take it to design level using free tools.. Should you need more info please email me [e-mail] Regards..Jay.

[@M7hero]

You have wrong connection in the nMOS device, the terminal of the npn should be connected to the drain of the nMOS and not the source.

[@sarveshsingh479]

thankyou sir

[@analoglayoutdesign2342]

Thanks for the feedback