HDL Verilog Project (with code) | Clock with Alarm | Xilinx Vivado

[@dr.ritamahajan9937]

Very well explained Arjun. God bless you with bright future.

[@ArjunNarula1122]

Thank you ma'am!!😇😇

[@adityamehta4147]

Descriptive & well explained working of the project👌🏻

[@ArjunNarula1122]

Thanks a lot , Aditya!!😊

[@yuktasachdeva7822]

Great initiative to share HDL Projects here😊 Well explained 👑

[@ArjunNarula1122]

Thanks Yukta!!

[@ishajain949]

Great Project with a detailed explanation of the working as well as the code Arjun✨

[@ArjunNarula1122]

Glad you liked it Isha . ✨✨

[@yuganshibharti3892]

Bohot badhiya Arjun!!! Keep on working hard 💥💥

[@ArjunNarula1122]

Shukriya Yuganshi !!!✨✨

[@pragatimali7623]

Hey.. I have done the same project but my output is not coming as you are showing. Can you please suggest me a way out

[@ArjunNarula1122]

@Ak Kumar , you asked for the Verilog book in live chat. Verilog HDL Book-@t Verilog with Digital Design - @t

[@ArjunNarula1122]

Please find the code in the link description. Any suggestions or queries are most welcomed. Other Projects- ►Traffic Light Controller in Verilog - kzbin.info/www/bejne/j6Wan6Jsp9x2jM0 ►Round Robin Arbiter in Verilog - kzbin.info/www/bejne/jmfSe6Ftp55gbtU ►Vedic Multiplier in Verilog - kzbin.info/www/bejne/bH6Wn6yvhsujfrc ►Clock with Alarm in Verilog - kzbin.info/www/bejne/poXOYntrZcprmKs ►Washing Machine in Verilog - kzbin.info/www/bejne/n3LSmmygid-rmas ►N bit Multiplier in Verilog - kzbin.info/www/bejne/op7ddJeua8yemrc ►PWM Shift Register in Verilog - kzbin.info/www/bejne/hqucpIOcobCjjsU ►Vending Machine in Verilog - kzbin.info/www/bejne/qnvGYZWid6mFsNE ►Hexadecimal Keypad Scanner in Verilog - kzbin.info/www/bejne/j2LGoWWhrNSma68 ►RAM - ROM Design in Verilog - kzbin.info/www/bejne/o2Kbiohvrc94irc

[@A_Trips]

In my Xilinx ISim simulator why *Alarm* ⏰ output signal is not shown?? Else everything is same with same code..

[@diwanshi6669]

Very well explained...hats off to u man💫

[@ArjunNarula1122]

Thanks Diwanshi !!

[@adityaagrawal8717]

Amazing video with step by step explanation

[@ArjunNarula1122]

Glad you liked it .😊

[@MoneyMachine68]

🔴🔴🔴 Why you added seconds in output and why not in input ???

[@atushgoel7823]

As ever a good Project that very well explained🔥

[@ArjunNarula1122]

Thanks Atush!!😊

[@ritikgupta8478]

Great explanation and amazing work 💯

[@ArjunNarula1122]

Thank you Ritik . ✨

[@devashishbawa8236]

Nice project !! Very well explained

[@ArjunNarula1122]

Thanks Devashish!! ✨

[@mehakjain1956]

Very well explained arjun🔥🤩

[@ArjunNarula1122]

Thanks for the verilog code Mehak!!! 🌟🌟

[@khushaljagtap4883]

Can this be implemented using FPGA hardware and if yes what would be the port mapping to FPGA?

[@parashgoswami7561]

Awesome work guys 🔥🔥

[@ArjunNarula1122]

Thanks 🔥

[@vimminarula5523]

God bless you nice project

[@ArjunNarula1122]

Thank you 😇

[@abhishekabhishek5944]

Indeed really intriguing !!! Keep posting :)

[@ArjunNarula1122]

Thank You!!

[@mithrharamakrishnan3563]

Thankyousoomuch..clear explanation 🤙🏻💥

[@Desi_Odyssey]

Commendable job guys

[@ArjunNarula1122]

Thank you!!

[@lakshin.2721]

Kuch samajh nahi aaya pr acha lga :)

[@ArjunNarula1122]

Thanks !!

[@adithyanayak4031]

Why u didn't take seconds as input. Why u took seconds as only output

[@raeleenkanda8270]

Amazing Explanation 💐💐

[@ArjunNarula1122]

Glad you liked it . ✨

[@mehakgoyal7173]

Great explanation!🔥

[@ArjunNarula1122]

Thank you . 😀

[@riswanamr4836]

Hello,how to get its project project report...please help

[@zainabqureshi5744]

Can this be implemented on fpga?

[@rohansalve976]

do we have to add numbers of inputs and outputs , like in project navigator when i create new project and select virtex 7, it asks inputs and outputs ,what do i write there?

[@ArjunNarula1122]

When you create the project , it asks input and output for the Verilog code , you could here write the input and output of the project mentioned at 2:53 in the video.

[@sparshgupta3922]

Very well explained!!

[@ArjunNarula1122]

Thanks!!

[@ronixbhaskar8263]

Bhai apne konsa fpga simulation kiya hai

[@ArjunNarula1122]

The default part and product family for the new project: Default Part xc7vx485tffg1157-1 Product: Virtex-7 Family: Virtex-7 Package: ffg1157 Speed Grade: -1

[@ronixbhaskar8263]

I didnt understand brother because I'm at beginner level

[@ArjunNarula1122]

So it is basically the default FPGA in the vivado project.

[@ayushmahendru1858]

Awesome project!!

[@ArjunNarula1122]

Thanks Ayush!!

[@BAEC_kiran]

can you explain the same code in model sim simulator

[@sehajpreet4570]

Great project🔥👌

[@ArjunNarula1122]

Thanks ✨

[@MrCyberAk]

pls.make separate detail video on simulation

[@shubhamsingh-pm3vq]

can u make a dada multiplier with verilog code ?

[@ArjunNarula1122]

Yes Shubham Singh dada multiplier is definitely on the list. Stay tuned and subscribe to the channel.

[@geetikabansal7311]

👍👍

[@harmanchawla33]

Video🔥

[@ArjunNarula1122]

Thanks 😊

[@aradhanamehta8767]

Well-done

[@enessml]

Amım 🔥

[@tallasravani7055]

code can be explained good

[@sanyamjain1617]

👍👍👏

[@1426__MOHITKONCHADA]

essss code ka link hoga tho b ejo

[@prashanthkondra3845]

i habit project on Digi Alaram Clock

[@cikudaniels]

Thankyou so much

[@prashanthkondra3845]

Hi Arjun

[@enessml]

Hi pırasa

[@prashanthkondra3845]

@@enessml can i get you cont details

[@karthikar908]

Can you send me your mail id pls.i have some doubts in simulation