Two flop synchronizers (synchronization) or Flip Flop Synchronizers / FIFO-part4

[@bharadwaj767]

even it is not guaranteed that we would get logic HIGH (2:07) after that clock period... it might go to 0 as well right please let me know if you have any insights on this

[@jayaramank3236]

good explanation thanks

[@abhinavsonkar2936]

Excellent explanation. Please keep uploading such videos.

[@KarthikVippala]

Hi abhinav , thanks for your support , please suggest topics you need , it will be helpful in preparing more such content, please do reply.

[@abhinavsonkar2936]

@@KarthikVippala If possible then please make videos on computer architecture from scratch.

[@KarthikVippala]

Thanks for suggesting , give me sometime I will do it for you , please do comment if you have doubts👍

[@sohamlakhote9822]

Great job bro!!! I understood many things by watching your 3 min video as compared to other videos which are 15-17 min long. Keep it up!!

[@KarthikVippala]

Thank you brother 🙏👊

[@77uu22]

Hi, One question on 2 flop synchronizer, the settling of metastability causes latency issue at the recever side, as for a signal changing from 0->1 at flop1 might settle to 1 or 0 before getting sampled by flop2, but will settle to value 1 in next clock So if it is settle in first clock the latency is 2 else the latency will be 3 How to update design to make this latency a fix value Considering both clock same frequency with phase difference

[@nareshthakur6087]

Hi In this example QA is changing from 0->1 and QB1 is settling to 1 so we are getting correct output at QB2. Suppose QB1 is settled to 0 (as it can go to either 0 or 1 from metastable state) then QB2 will get wrong output. Am I correct? can you please explain on this

[@KarthikVippala]

Hi Naresh , thanks for asking Yes you are absolutely correct , QB1 can go to zero , QB2 will be wrong . We cannot remove metastability , but we can reduce it, we can use handshake to check whether the output is correct or not , if it's correct we will not change otherwise we will discard it and resend the input. This will be slow but we need to add it for meeting design output. Hope this clears your doubt ,if you have any questions, feel free to comment. I am happy to help you 👍. Please do subscribe it will help me a lot 👍

[@prashantmata7709]

@@KarthikVippala Follow up question, So during metastability if the output resolves to a different state, then this synchronizer also fails? Am i correct?

[@KarthikVippala]

Yes prashant , you're correct Good luck, good health👍

[@vikasbansal4180]

@@KarthikVippala thanks for very good explaination of all concepts, i have 2 questions. 1. As synchronizer ensures no metastablity in o/p, it not ensure correct data sended, so "synchronize fail" may not be correct term?? right or wrong 2. How to check correct data got at o/p using handshake, i had seen that handshake video but answer was not there, can u please tell??

[@hgl9590]

@@KarthikVippala thanks for the nice explanation. Do you have materials about such handshake mechanism?

[@NDUnq-p6n]

Well explained. But what if after the first flops, the metastability signal GOES DOWN, and 2nd flip flops can capture its high value, meaning after signal go through two flip flops, it's stable but we can sure it's 1 or 0.

[@saurabhkatre7355]

Excellent. I have one doubt. Is the output QB1 after metastability period will always settle to logic 1 (so as to follow input)? Or can it also go to logic 0.

[@KarthikVippala]

Saurabh , thanks for asking the question. Synchronizers do not ensure that data get across , but they ensure that signal don't end up in Metastability. So output is unpredictable. For understanding purpose I have shown it like that in the diagrams. Hope this clarifies your doubt. Please do subscribe it will help me a lot to keep going , thanks for asking.

[@sagarborad5746]

@@KarthikVippala Karthik, More stress should be put on this line "Synchronizers do not ensure that data get across" if correct data doesn't get across then how good synchronizer is ?

[@KarthikVippala]

@@sagarborad5746 sure sagar will make short video so that people won't have this confusion. good luck & great health:)

[@AhmedMohamed-km6jg]

nice work , hard topic in short time

[@KarthikVippala]

Namaskaram 🙏 Ahmed, thanks for support , good luck, great health 👍😊

[@danielarthur7739]

I have a question, Im using clock gating in my design. My question is: the clock gating should affect the dual flop synchronizer or the synchronizer must have the free clock always?

[@AjayMukeshMehtaMVD]

I've one doubt, like QB can QC also go to metastable state here? As QB act as input to FF(C) and QB is in metastable state at posedge of clock so FF(C) output also go to metastable state.

[@KarthikVippala]

Hey Ajay , thanks for asking the question , now coming to explaination , there is a chance that QC can go to Metastability if output of QB is still in metastable condition even after one clock period, if output of QB settles to 0 or 1 then there will be no metastability . Hope this clears your doubt,if you have any doubts please feel free to comment. Please do subscribe it will be helpful for me 👍

[@1000manmath]

@@KarthikVippala In such cases, will it be advised to use more than two FlipFlops?

[@KarthikVippala]

@@1000manmath you are correct we need to use two flip flops for synchronization

[@karanrawat9674]

@Karthik Vippala I dont understand from where rd and write pointer comes in this,if destination clock captures same data 2times as its on high speed how captured data is correct.. So let's say source side if data is 1010 destination will capture 11001100? Please clear my doubt

[@tomcat1184]

thank you for your wonderful explanation

[@KarthikVippala]

Glad it was helpful!

[@nida4404]

If we have 2 clock domain synchronous then what value we take in d flipflop

[@rakeshpookkotte1867]

Hello , can you suggest me a method where I can increase my clock frequency from 70MHz to 100MHz

[@PranavSingh-ur9ic]

how do we know that data will get stable in one clock cycle (i mean before next clock edge)??

[@bharadwaj767]

and even it is not guaranteed that we would get logic HIGH (2:07) after that clock period... it might go to 0 as well right please let me know if you have any insights on this

[@bhoomikasbidari3936]

Sir , Please explain about how many synchronisers to use based on situation. Like you have explained about 2 stage , please explain multistage synchronisers.

[@KarthikVippala]

Hi, mostly 2 stage is enough, but if it's failing we will tripple flop , and this is the max we go in the design. Thanks for asking 🙏

[@bhoomikasbidari3936]

@@KarthikVippala Thankyou so much sir. Excellent explanation ☺️

[@neeleshranjan7827]

sir, what happens when the value after metastability settles to 0 in this case, then my output would be wrong. How to eliminate this problem?

[@syamsundarmalla]

Sir,if we want pass data from slow speed clock high then is this 2 flop synchronizer is useful or not

[@08bharadwaj]

Hello, considering the difference in frequency bw wr and rd is huge. Is there any issue if pointer values get missed after synchronization.

[@KarthikVippala]

Hey Bhardwaj thanks for asking the question, no there will be no issues due to synchronization of rd and wrptrs, there will be delay in the red or wr to happen but values will be correct. Good luck, good health 👍

[@karanrawat9674]

@@KarthikVippala I dont understand from where rd and write pointer comes in this,if destination clock captures same data 2times as its on high speed how captured data is correct.. So let's say source side if data is 1010 destination will capture 11001100? Please clear my doubt

[@GG90526]

what is the use of 3 flop synchronizer and where we are using it? thank you in advance.

[@KarthikVippala]

It is used CDC , if two flop fails to give the results . Thanks for asking, good luck, good health 👍

[@GG90526]

How to ensure that 2 flop synchronizer is not sufficient?

[@KarthikVippala]

Trial and error is the best option .

[@GG90526]

@@KarthikVippala thank you for your quick response.. hope u doing well.😀😀

[@KarthikVippala]

@@GG90526 your welcome 👍

[@nephewniece3312]

Hi, I've one doubt, is it true path or false path between B - C??

[@KarthikVippala]

It is true path ,and will be considered 👍

[@riffattahira4839]

well explained

[@KarthikVippala]

Thank you

[@nisargadk3672]

can u please make a video on design of synchronisers using verilog coding?

[@KarthikVippala]

Namaskaram nisarga🙏 , thanks for asking , I will make video but it will take time, good luck & great health 👍😊

[@PremKumar-jq3wg]

why two flop synchronizers, why not 3-4 flop synchronizers, if you say it depends upon MTBF and frequency, then there is a certain limitation that flop should add that frequency exceeds certain limitations

[@uday5786]

Can u do video on toggle synchronizer

[@KarthikVippala]

I will do it , but need some time ,👍

[@KarthikVippala]

Hey uday , check the channel for the video 👍

[@adityagautam7276]

Why the accent

[@KarthikVippala]

Just so that no one finds it's me😁

[@riffattahira4839]

well explained

[@KarthikVippala]

Thank you for your feedback and support 🙏