Operations in sensitivity lists !! always @(a && b) .....

This is the common mistake , most of beginners do , I wanted to create awareness to avoid such practise in design.
#programming #tech #vlsi #code #rtl #verilog
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[@golinagasandesh4464]

Nice video 🤩. Never thought of it!

[@KarthikVippala]

Thank you🙏

[@puneetkumar2662]

Could you please upload videos little frequent It will help alot thanks 😊😊😊

[@KarthikVippala]

Sure 👍

[@PilatesinSacramento]

I’m just learning Verilog now after writing in VHDL many, many years ago. Super helpful stuff, man!

[@KarthikVippala]

Thank you🙏🤗

[@abdulrahimnaser]

Hi, thanks for your video, have you got any source of something kind of like digital design interview question bank for big tech companies?

[@darkeagle999]

Why not use * instead

[@KarthikVippala]

Yeah we can use for combo logic, and it has it's problem while using a function. Better to use always_combo, always_latch for combo logic, 🤗