Sta latch based designs

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vlsideepdive

vlsideepdive

Күн бұрын

Пікірлер: 4
@rahulbhat3409
@rahulbhat3409 Жыл бұрын
Thanks for the lecture. Please help clarify this query. The max delay with which data can arrive at latch is described to be the transparent period of latch - which I understand , but wouldn't this also be dictated by the delay of next stage combinational cloud i.e it should be able to meet setup for next flop ?
@vlsideepdive
@vlsideepdive Жыл бұрын
Yes, you are right. Both paths need to meet setup and hold. But the advantage is that you have the flexibility that you can borrow from the next level and use it here if the next level has a lesser delay.
@anirudhabehera5716
@anirudhabehera5716 8 ай бұрын
can you discuss a problem with what happens if the latch is a Look-up Latch? FF1 to latch Td is 40ns and latch to ff2 is 60ns, Total Period is 100ns. How will this scenario work?
@vikasbansal4180
@vikasbansal4180 Жыл бұрын
Thank u sir
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